Multiple cylinders detection from large-scale and complex point clouds is a historical but challenging problem, considering the efficiency and accuracy. We propose a novel framework, named slicing-tracking-detection (STD), that detects multiple cylinders accurately and simultaneously from point clouds of large-scale and complex process plants. In this framework, the 3D cylinder detection problem is reformulated as a cylinder ingredients tracking task based on multi-object tracking (MOT). First, we generate slices from the input point cloud, and render them to slice sequence. Then, the cycle of a cylinder is modeled with a Markov Decision Process (MDP), where the ingredient is tracked with a template and the miss tracking is associated with ingredient proposals through reinforcement learning. Finally, by applying MDP for each cylinder, multiple cylinders can be detected simultaneously and accurately. Extensive experiments show that the proposed STD framework can significantly outperform the state-of-the-art approaches in efficiency, accuracy, and robustness. The source code is available at http://zhiyongsu.github.io.

A practical RTL level testability analysis methodology is presented in the paper. Both RTL models and functional verification patterns are used in the RTL testability analysis. An RTL fault simulator which is the core of the methodology, is developed to support RTL testability analysis. It is able to generate quantitative RTL fault coverage and provide information for test pattern improvement to improve fault coverage and design modifications to improve testability at the RTL level. Experimental results show that RTL fault coverage is quite close to fault coverage achieved at the gate level when designs are completed and mapped to a technology library. The results also show that effort to improve fault coverage at the RTL level very likely results in corresponding improvement of fault coverage at the gate level. An investigation of some of the causes of difference between RTL fault coverage and actual gate level fault coverage is also reported in the paper.

A structure for testing the interconnect faults and measurement of discrete components on mixed-signal boards is proposed. The structure requires one analog pin in addition to the IEEE 1149.1 pins on each mixed-signal IC. Simulation results are provided to show the accuracy of the metrology.

Simulation data are presented for eleven benchmark circuits to show how test pattern correlation in a scan-path design circuit adversely affects delay fault coverage, and to demonstrate that most undetected delay faults caused by correlation of test patterns are close to the outputs of latches. Topology-based latch correlation measures are introduced and used by a companion latch arrangement algorithm to guide the placement of latches in a scan-path design, with the objective of minimizing the effect of correlation and maximizing the coverage of delay faults. Simulation results with benchmark circuits indicate that the scan-path found by the algorithm clearly achieves better delay fault coverage than a scan-path having no deliberate arrangement. The data also indicates that the algorithm is most effective in covering delay faults that are located nearest the latch outputs of the circuit. The approach has an advantage over other arrangement schemes in that it is simple to implement and does not require significant computational time even for large circuits.>

In this paper, we introduce a new test generation algorithm for testing ate delay fault. The main new feature of the algoritfm is that it uses auantitanve information about detection threshold Fd robustness to guide its choice of the fault sensitizabon path and the associated line j-ustifications. The. algorithm attempts. to reduce the detectnon threshold and increase the quanbtabve robustness of the test s. Thus, with this new algorithm, we are able to show Etest pattern sets generated by the algorithm achieve better fault coverage, detection threshold and robustness than those that are generated randomly.

Experimentaldata is presented for eleven benchmark circuits to show how test pattern correlation in a scan-path design circuit adversely affects delay fault coverage, and to demonstrate that most undetected &lay faults caused by the test pattern correlation are close to latch outputs.Topology-based latch correlation measures are introduced and used by a companion latch arrangement algorithm to guide the placement of latches in a scan-path &sig~with the objective of minimizing the effect of the test pattern comelation and maximizing the delay fault coverage.Experimental results with benchmark circuits indicate that the scan-path found by the algorithm clearly achieves better delay fault coverage than a scan-path having no deliberate arrartgemeng and, in fac~achieves nearly the coverage that can be gotten by unrestricted application of the test vectors to the circuit without a scars-path.The data also indicates that the algorithm is most effective in covering delay faults that are located nearest the latch outputs of the circuit.The approach has an advantage over other arrangement schemes in that it is simple to implement and does not require significant computational time even for large circuits.

Test methodologies for delay faults usually observe output patterns at a single observation time, and the same observation time is used for all faults in the circuit under test. In this paper we show that use of a single observation time is not advantageous for testing delay faults, and we are able to show that the detection threshold can be dramatically improved by using a testing methodology that allows variable, fault-dependent and output-dependent observation times. A “waveform-type” simulation method is used for calculating detection thresholds for definitely detectable faults. Statistical distributions of delay fault detection thresholds are presented for ten benchmark circuits.

A hierarchical leakage fault analysis methodology is proposed for IDDQ (quiescent power supply current) testing of VLSI CMOS circuits. A software system, QUIETEST, has been developed on the basis of this methodology. The software can select a small number of test vectors for IDDQ testing from the provided functional test set. Therefore, the total test time for IDDQ measurements can be reduced significantly to make IDDQ testing of VLSI CMOS circuits feasible in a production test environment. For two VLSI circuits QUIETEST was able to select less than 1% of functional test vectors from the full test set for covering as many leakage faults as would be covered if IDDQ was measured upon the application of 100% of the vectors.>

A problem involving the arrangement of latches in a scan-path design to improve the coverage of delay faults is described. The problem is NP-hard, and a heuristic algorithm is introduced for solving this arrangement problem. A necessary and sufficient condition is also given to determine whether there is a scan path to implement a given delay-fault test pair. Only LAM (latch-arrangement-mapping) implementable test pairs need to be simulated by a delay-fault simulator for a semi-completed LSSD (level-sensitive-scan-design) circuit. Preliminary experimental results show that the proposed algorithm can find a LAM with better fault coverage than a randomly selected ones.>

A self-learning algorithm called DYTEST, which uses a dynamic testability measure (DTM) to accelerate test generation, is presented. DYTEST's DTM guides the choice of a potential main sensitizing path during test generation. A full-logic value label backward implication creates estimates of logic values for the primary inputs. Dependent and k-limited backtracks are used to further reduce the number of backtracks.>

A new, simplified waveform method is presented for delay fault testing. The method enables accurate calculation of a delay fault detection threshold for definitely detectable faults, and a delay fault range for possibly detectable faults. The method is shown to correctly classify definitely detectable faults which are mis-classified by methods recently reported elsewhere [1,2]. A quantitative delay fault model with variable fault size is used, and the effect of the delay fault is explicitly described by the new waveform method. The calculation of the detectable delay size threshold occurs in linear time for any definitely detectable fault.

A test generation algorithm for stuck-open faults in CMOS combinational circuits is presented in the paper. A two pattern test, e.g., an initializing input pattern T1 and a test input pattern T2 can be generated at the same time. It is shown that the test {T1,T2} generated using the algorithm is a robust test.