As the number of cores on a chip increases, Networks-on-Chip (NoCs) that connect many cores would face long links to reduce hop counts. The long links become bottlenecks in terms of both energy and RC delays as technology advances. To alleviate the negative impact of long links, we propose decentralized routers for NoCs. A decentralized router consists of multiple submodules that are positioned on a link, and hence the long links are segmented. Furthermore, we illustrate the design of an entire network that uses decentralized routers to obtain a good tradeoff between hop counts and wire delays per hop. Decentralized routers are effective especially in high-radix topologies, such as the flattened butterfly, and energy-delay product is reduced by greater than 60 percent. As NoCs become larger and more complex, the benefit of the decentralized routers will become more significant.

Technology scaling makes designers face difficulties dealing with wire delay of long global interconnects, especially for high-radix networks. In this context, we propose decentralization of on-chip packet routers. A decentralized router consists of submodules, each of which has particular functionality and they are scattered on a link, thereby long wires are segmented. Our starting point is from a conventional router architecture, and we illustrate four case studies to generalize our proposal. We also propose a new buffer design and how to balance pipelines of a router. A proof-of-concept is shown in 28-nm process technology. Our results demonstrate that the decentralization of an on-chip router enables Link Traversal (LT) stages to be eliminated, and the critical path delay is improved by up to 45% with the reduced area compared with a conventional router. As technology advances, the benefit of the decentralized routers become more substantial in the nano-scale era.

Power consumption of Network-on-Chip (NoC) is becoming more important in many core processors. Input buffers utilized in routers consume a significant part of the total power of NoCs. In order to reduce this power consumption, a novel power efficient memory called Marching Memory Through type (MMTH) is introduced. By connecting transparent latches in tandem, MMTH achieves high speed operation with a low power consumption. MMTH, however, requires a certain overhead at read operation, and hence we propose a latency reduction scheme based on the look-ahead routing. The proposed router was designed in Renesas's 40nm process and compared with a standard router using conventional register-based FIFOs in terms of the network performance, application performance, and power consumption. The result of evaluation shows that the proposed router reduces the power consumption by 42.4% on average at 2GHz and the expense of only 0.5-2.0% performance overhead.

No abstract available.

Ray tracing is a global illumination based rendering method widely used in computer graphics. Although it generates photo-realistic images, it requires a large number of computations. In ray tracing, the ray-object intersection test is one of the dominant factors for the processing speed. To accelerate the intersection test, we propose a new method based on a plane-sphere intersection algorithm, and show a hardware system using an FPGA. The computations used in the method are highly pipelined and parallelized by optimizing the balance between the computation speed and the memory data bandwidth. As a result, the prototype makes full use of 512 DSP cores built in Xilinx Vertex-4 SX FPGA, and the average utilization of the DSP cores is close to 90%. The simulation results show that the proposed system running at 160MHz performs the intersection test a few hundred times faster than a commodity PC with a 3.4GHz Pentium 4

Clustered architectures which intend to process data within a localized PE are one of the approaches to increase the performance under the difficulties of the wire delay problems. The performance of clustered architectures depends on the amount of parallel execution of instructions and the amount of inter-PE communication to synchronize dependent instructions. In this paper, we propose an arrangement of PEs cooperating with the adjacent PEs by means of adding communication structures between the adjacent PEs in order to relax the inter-PE communication and workload imbalance in an effective manner. We evaluate the proposed configurations and compare them with the existing one so far considered. The results show that the proposed adjacent forwarding network configuration with the instruction steering scheme that concerns both the register fanout and available free register can achieve higher instructions per clock (IPC) with the small number of registers per PE than the other configurations.

Vector quantization (VQ) is an attractive technique for lossy data compression, which is a key technology for data storage and/or transfer. So far, various competitive learning (CL) algorithms have been proposed to design optimal codebooks presenting quantization with minimized errors. However, their practical use has been limited for large scale problems, due to the computational complexity of competitive learning. This work presents a parallel competitive learning algorithm for fast code-book design based on space partitioning. The algorithm partitions input-vector space into some subspaces, and independently designs corresponding subcodebooks for these subspaces with computational complexity reduced. Independent processing on different subspaces can be processed in parallel without synchronization overhead, resulting in high scalability. We perform experiments of parallel codebook design on a commodity PC cluster with 8 nodes. Experimental results show that the high speedup of the codebook design is obtained without increase of quantization errors.

In unspecified bit rate (UBR) service provided by ATM networks, users send cells into networks with no feedback; no guarantee cells may be dropped during congestion. This paper describes a congestion control scheme using active network technology to avoid congestion in a conventional ATM network. The Ants routing algorithm for congestion control associated with active networks is implemented. The routing algorithm uses information that is monitored and revised according to the congestion status of output ports and sends commands to other switching elements. The active switching elements share information about traffic levels of the interconnection network and reciprocate customized programs for rerouting cells in the presence of congestion at a switching element's output ports. As a result, it is possible to build an active switching network that can avoid congestion in a conventional ATM network.

The limited amount of instruction-level parallelism inherent in applications is a limiting factor for improving the performance of most conventional microprocessors. A promising solution to overcome this problem is to exploit coarser granularities of parallelism. In this paper, we propose exploiting loop-level parallelism in a multithreaded fashion. We use the Shift Architecture as a baseline architecture, with improved compiler support and register file. The compiler converts iterations of a loop into threads, to be executed by multiple processing elements. The hardware provides a selective register shifting mechanism in order to allow the execution of loops containing loop-carried data dependences, which are very difficult to execute by using conventional architectures. In this paper, we simulate and discuss the parameters of major importance for the implementation of this architectural approach. Our initial results show that, on two simple numerical benchmarks, a considerable amount of iteration overlapping can be potentially achieved by an implementation of the Shift Architecture, in comparison with a multiprocessor machine.

This paper proposes an intelligent memory architecture for photo-realistic image synthesis, named 3DCGiRAM. The 3DCGiRAM has a hardware-accelerated 3D line generator which finds objects that are likely to intersect traced rays. It also has functional memory cells, each of which is composed of graphics logic and its local memory to detect intersecting objects and to calculate intensities. A distributed frame buffer is employed to alleviate the access conflicts of functional cells to the frame buffer as well as to compose globally illuminated intensities at screen pixels. As the graphics processing capability is localized to data in the 3DCGiRAM through memory-logic merged LSI technology, a scalability and modularity similar to those of conventional memory modules can be expected. The experimental results show that a single 3DCGiRAM module running at 200 MHz with a memory bandwidth of 6.4 GB will be able to synthesize a ray-traced walk-through animation at a rate of one frame per second.

Wireless media, which is commonly used for advertising purposes, should be constructed in a manner which reduces the required access time and the cost for the receiver. Two families of orthogonal codes are presented as a means to deliver information based on CDMA technology. The data stream that contains pages and links is coded with a unique set of Walsh-Hadamard (WH) functions, while the whole data stream of a particular base station is coded using the Bent sequence, another class of binary coding sequence. Numerical results are presented and they show that a system using Bent coding exhibits a significant improvement in performance in terms of the bit error rate and potential number of simultaneous users in comparison with other sequences.

No abstract available.

We propose an artificial neural system that forms memory by receiving input vectors obeying an unknown nonstationary probability density function (PDF). The system consists of a set of neural vector quantizer (NVQs), each of which can approximate nonstationary PDFs. Each NVQ exclusively learns a stationary piece of the nonstationary PDF and stores its approximated representation, where the nonstationary PDF consists of some stationary pieces. Experimental results show that the system has functions "memorization", "retention", and "recall" of information which is required in memory systems. The results also illustrate that the system receives inputs from a nonstationary PDF and stores statistical information by distributing it equally over the system. The system can also be used to model nonstationary phenomena. This ability is desirable for various applications, for example, process control, economical modeling, etc.

Recent high-performance microprocessors have two or more functional units (FUs) to exploit instruction-level parallelism. To make full use of this capability, multiport register files are generally used. However, conventional multiport register files need a considerable amount of hardware. This paper proposes a multiport register file scheme, which uses time-division multiplexing with wave pipelining in order to save the needed hardware resources. For adjusting propagation delay timings, we develop a tool which automatically inserts dummy buffers into combinatorial logic.

Though indispensible for artificial intelligence (AI), symbols have not always been processed at a satisfactorily high speed by tools from AI. The authors introduce a new scheme and its hardware support for the parallel processing of symbols, using a functional language similar to Lisp. The structure of programs and data in this language is stored as lists with binary-tree links. The parallel processing is composed of the static analysis and dynamic synthesis of this structure. Both processes are supported by a multiple processing element (MPE) system arranged in a rectangular-lattice network topology. MPE is superpipelined in the static analysis to transform the structure and is controlled in a parallel-superpipeline fashion in the dynamic synthesis to evaluate the transformed structure. The symbolic processing by MPE needs less time and memory than usual processing methods. Hence, the scheme is an effective way to organize a powerful AI machine.

A routing control method called potential routing is proposed for packet communication in computer networks. Potential routing models a computer network as an electrical circuit, and performs packet routing according to the potential differences between adjacent nodes. The node potentials are first given by Kirchhoff's law and are then dynamically adjusted according to the traffic situation. Potential routing can be applied to arbitrary network topologies; it takes account of the global network topology in determining the route. The routing table is easily and therefore quickly computed by Kirchhoff's law, by solving simple simultaneous equations; no convergence problem arises. Moreover, potential routing does not involve the ping-pong (loop) problem. It is verified by simulation that potential routing shortens transmission delays, especially when the traffic is heavy or unbalanced.>

This paper deals with Lips programs whose forms are more general than previous programs. Extended parallel pipeline execution is explained for the whole of a compiled Lisp program. The extended parallel pipeline execution includes fully parallel/semiparallel execution by using one-dimensional processor arrays (ODPAs). The tradeoff between the scale of the ODPA and the execution time of the compiled Lisp program is examined.>