A new algorithm for implementing the two's complement multiplication of an m × n bit number is described. By interpreting certain positive partial product bits as negative, a parallel array is developed which has the advantage of using only one type of adder cell. A comparison with the Pezaris and Baugh-Wooley arrays is presented, showing that the new array is as fast as the Pezaris array and uses less hardware than the Baugh-Wooley implementation.

The operating characteristics of a typical single-node hierarchical element in a multiprocessor network such as might be used for process control are described, and the class of scheduling problems arising from the use of such a network is discussed and related to similar problems which have been reported in the literature. Two measures of system performance are then defined: the "settling time," defined as the maximum of the finishing times of all jobs when a set of jobs is initiated once in the network, and the "steady-state service," a related performance index for the case where jobs are initiated on a periodic basis. Finally, a simulation model is used to evaluate the operating characteristics of the hierarchical network using the two metrics in conjunction with several synthetic workloads; a general optimization procedure is shown to lead to values of scheduling parameters which are close to optimal even for network workloads with many degrees of freedom (i.e., when many computers are initiating jobs).

The basic goal in the design of computer control units is the efficient, high-speed allocation, orchestration, and synchronization of the computer resources. The key concept to meeting the above requirements is the continual optimization of the control structure during the design process. This paper defines an approach to control optimization which is independent of the particular control structure.