A wide tuning range LO generation architecture for software defined radio is presented. A dual VCO approach followed by a programmable divider chain based on high-speed dynamic CMOS latches provides full rail-to-rail operation with low power consumption. The 1.2V 90nm CMOS implementation achieves a VCO tuning range between 6 to 13.6GHz for a power consumption between 3.5 to 13.4mW and phase noise figure of merit of 182dBc/Hz measured at 3MHz offset from a 12GHz carrier. The VCO-multiplexer and divider chain consumes between 5.9 to 8.1mW for this frequency range.

Substrate noise problems in a system-on-a-chip hamper the smooth cohabitation between analog and digital circuitries on the same die. Solving those problems will shorten the time to market. This paper presents a methodology that gives designers the necessary insight to solve this substrate noise problem. The methodology combines the strengths of the electromagnetic simulator, the parasitic extractor, and the circuit simulator. Its main assets are the ease of use, an acceptable simulation time, and a good accuracy. Moreover, this methodology does not need doping profiles that are hard to get hold off. The proposed methodology is demonstrated on two challenging examples: a 48-53-GHz LC voltage-controlled oscillator and a dc-to-5-GHz wideband receiver designed, respectively, in a 0.13-mum and a 90-nm CMOS technology. The substrate noise coupling mechanisms are revealed for both examples in a simulation time of less than 2 hours. The methodology is successfully validated by measurements performed on real-life prototypes of those examples with an accuracy of 1-2 dB.

Modern integrated radio systems require highly linear analog/RF circuits. Two-tone simulations are commonly used to study a circuit's nonlinear behavior. Very often, however, this approach suffers limited insight. To gain insight into nonlinear behavior, we use a multisine analysis methodology to locate the main nonlinear components (e.g. transistors) both for weakly and strongly nonlinear behavior. Under weakly nonlinear conditions, selective Volterra analysis is used to further determine the most important nonlinearities of the main nonlinear components. As shown with an example of a 90 nm CMOS wideband low-noise amplifier, the insights obtained with this approach can be used to reduce nonlinear circuit behavior, in this case with 10 dB. The approach is valid for wideband and thus practical excitation signals, and is easily applicable both to simple and complex circuits

Analyzing the stability of an analog circuit is an important part of the circuit design. Several commercial simulators are equipped with special stability analysis techniques. Problems arise when your design kit does not support such simulator. Another issue is when the designer wants to get insight into the sources of the instability to propose a stabilization. This can be done through analyzing the open-loop or the closed-loop transfer function of the circuit. The aim of this paper is to propose an automated analysis method which identifies the nodes to be considered for stabilization. The method does not need to break feedback loops or to manipulate netlists. It only uses AC simulations and does not require the full modified nodal equations. The method is illustrated on 3 design examples: a voltage controlled oscillator (VCO), a reference bias circuit and the common-mode feedback network in a gm-C filter

Design of electrical systems demands simulations using models evaluated in different design parameter choices. To enable the simulation of linear systems, one often requires their modeling as ordinary differential equations given tabular data obtained from device simulations or measurements. Existing techniques need to do this for every choice of design parameters since the model representations do not scale smoothly with the external parameter. The paper describes a frequency-domain identification algorithm to extract the poles and zeros of linear MIMO systems. Furthermore, it expresses the poles and zeros as trajectories that are functions of the design parameter(s). The paper describes the used framework, solves the starting-value problem, presents a solution for high-order systems and provides a model-order selection strategy. The properties of the algorithm are illustrated on microwave measurements of inductors, a variable gain amplifier and a high-order SAW-filter. As shown by these examples, the proposed identification algorithm is very well suited to derive scalable, physically relevant models out of tabular frequency response data.

Multicarrier modulation schemes are widely used in several digital telecommunication systems, such as Asymmetric Digital Subscriber Lines (ADSL) and Wireless Local Area Network (WLAN) based on Orthogonal Frequency Domain Multiplexing (OFDM). An estimate of the Bit-Error-Rate (BER) degradation due to non-idealities in the transceiver (e.g. nonlinear distortions in the analog front-ends, digital clipping,...) is much more complicated in a multicarrier system than in a single-carrier system due to the large number of carriers and the huge number of possible transmitted symbols. This paper proposes a method for estimating the BER of such OFDM modulation schemes in a CPU time that is two orders of magnitude smaller than a Monte-Carlo method, as confirmed by simulations on a 5 GHz IEEE 802.11 WLAN receiver front-end.

The explosion of the telecommunications market requires miniaturization and cost-effective realization of the front-ends of transceivers for digital telecommunications. New architectures must therefore be simulated at high level. Current methodologies and corresponding tools suffer from common drawbacks, such as lower accuracy, slow simulation speed, etc. A new methodology has been developped for the efficient simulation, at the architectural level, of mixed-signal front-ends of digital telecom transceivers. The efficient execution is obtained using a multi-rate, multi-carrier signal representation together with a dataflow simulation scheme which switches dynamically towards the most efficient signal processing technique available. An implementation of this methodology shows both excellent runtimes and a high accuracy.

A major problem when designing infinite impulse response (IIR) filters in the complex domain is ensuring that the filter is stable, especially when the IIR filter approximates the inverse of a non-minimum phase system, as is often the case for equalisation filters. Adding delay to the target frequency response can result in a stable filter, but up to now selecting that delay has been a matter of trial and error. This paper presents an automated method for finding this delay.