EDBT 2026 Demo / reviewers in the wild / expert
He Wang 0028
dblp:01/6368-28
· DBLP profile ↗
5ranked-venue papers
1as first author
4since 2021 · last 2026
0000-0003-0276-2036ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 since 2021Artificial intelligence and machine learning · 2 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | CIM-Tuner: Balancing the Compute and Storage Capacity of SRAM-CIM Accelerator via Hardware-mapping Co-explorationabstractAs an emerging type of AI computing accelerator, SRAM Computing-In-Memory (CIM) accelerators feature high energy efficiency and throughput. However, various CIM designs and under-explored mapping strategies impede the full exploration of compute and storage balancing in SRAM-CIM accelerator, potentially leading to significant performance degradation. To address this issue, we propose CIM-Tuner, an automatic tool for hardware balancing and optimal mapping strategy under area constraint via hardware-mapping co-exploration. It ensures universality across various CIM designs through a matrix abstraction of CIM macros and a generalized accelerator template. For efficient mapping with different hardware configurations, it employs fine-grained two-level strategies comprising accelerator-level scheduling and macro-level tiling. Compared to prior CIM mapping, CIM-Tuner’s extended strategy space achieves 1.58× higher energy efficiency and 2.11× higher throughput. Applied to SOTA CIM accelerators with identical area budget, CIM-Tuner also delivers comparable improvements. The simulation accuracy is silicon-verified and CIM-Tuner tool is open-sourced at https://github.com/champloo2878/CIM-Tuner.git. Jinwu Chen, He Wang 0028, Zhe Jiang 0004, Jun Yang 0006, Xin Si, Zhenhua Zhu 0002 |
DATE | 3 |
| 2026 | Switcher: Adaptive framework for unified and customized multi-modal object tracking
He Wang 0028, Tianyang Xu 0001, Zhangyong Tang, Xiaojun Wu 0001, Josef Kittler |
Pattern Recognit. | 1 |
| 2026 | An LSGQ-FFS Framework for Adaptive Optimization of Hybrid INT-CIM ArchitectureabstractHybrid computing-in-memory (CIM) has recently gained significant attention due to its ability to leverage the strengths of both digital CIM (DCIM) and analog CIM (ACIM). The multibit fusion (MF) scheme enhances energy efficiency by fusing low-bit results, which typically require multiple read-out cycles, into a single-cycle read out. However, the relationship between hybrid INT-CIM circuit design and network performance based on the MF scheme has not yet been systematically explored. In addition, we investigate how different MF configurations affect the performance of various neural networks. To address this gap, we first propose a less-significant group quantization (LSGQ) model, which defines and explores the design space of hybrid INT-CIM. Second, we develop a FastFuse-Search (FFS) algorithm, which optimizes configurations for different networks to strike a better balance between model accuracy and energy efficiency. Based on the experimental results, some key considerations on hybrid CIM design are derived. FFS yields a$1.72\times $energy-efficiency boost with negligible accuracy loss. Finally, we fabricate a 28-nm hybrid INT-CIM test chip, achieving 59.74 TOPS/W and 0.96 TOPS/mm2, with performance metrics of 23.21 perplexity for GPT-2, 68.69% accuracy for ResNet18, and 80.53% accuracy for ViT. Shaochen Li, Xi Chen 0107, Yujia Xiong, Lingyi Kong, He Wang 0028, Tianhui Jiao, Yan Yan 0030, Xin Si |
IEEE Trans. Very Large Scale Integr. Syst. | 6 |
| 2025 | Modeling of Less-Significant Group Quantization for Hybrid CIM ArchitectureabstractHybrid computing-in-memory (CIM) has gained growing interest in recent times due to its ability to combine the strengths of both digital CIM (DCIM) and analog CIM (ACIM). The Multi-Bit Fusion (MF) scheme enhances energy efficiency by fusing low-bit results, which would typically require multiple readout cycles, into a single-cycle readout. However, the relationship between hybrid INT-CIM circuit design and network performance based on the MF scheme has yet to be systematically explored. To fill this gap, a less-significant group quantization (LSGQ) model is proposed, defining and exploring the hybrid INT-CIM design space. Experimental results demonstrate up to 1.83x improvement in energy efficiency with minimal impact on performance. A 28nm hybrid INT-CIM test chip is fabricated, achieving 52.16 TOPS/W, 0.96 TOPS/mm2, with respective performance metrics of 48.58 perplexity for GPT-2, 75.51% accuracy for ResNet18, and 81.5% accuracy for ViT. Shaochen Li, Xi Chen 0107, Lingyi Kong, He Wang 0028, Yi Yang 0001, Xin Si |
ISCAS | 4 |
| 2015 | Saliency detection via Cellular AutomataabstractIn this paper, we introduce Cellular Automata-a dynamic evolution model to intuitively detect the salient object. First, we construct a background-based map using color and space contrast with the clustered boundary seeds. Then, a novel propagation mechanism dependent on Cellular Automata is proposed to exploit the intrinsic relevance of similar regions through interactions with neighbors. Impact factor matrix and coherence matrix are constructed to balance the influential power towards each cell's next state. The saliency values of all cells will be renovated simultaneously according to the proposed updating rule. It's surprising to find out that parallel evolution can improve all the existing methods to a similar level regardless of their original results. Finally, we present an integration algorithm in the Bayesian framework to take advantage of multiple saliency maps. Extensive experiments on six public datasets demonstrate that the proposed algorithm outperforms state-of-the-art methods. Yao Qin 0001, Huchuan Lu, Yiqun Xu, He Wang 0028 |
CVPR | 4 |