EDBT 2026 Demo / reviewers in the wild / expert
Sunil R. Das
dblp:01/684
· DBLP profile ↗
13ranked-venue papers
6as first author
0since 2021 · last 2018
0000-0002-7988-1298ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 6 · 1 first-authorHuman-computer interaction and ubiquitous computing · 4 · 3 first-authorDatabases, data management, data science and information retrieval · 2 · 2 first-authorApplied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Memory systems · 60% Integrated circuit design · 30% Energy-efficient computing · 9% | |
| Theoretical computer science
1 paper |
Logic in computer science · 100% |
Topics — the 7 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › memory circuit design
memory cell design |
0.3 | 1 | 2018 | Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Memory systems › emerging memory technologies
memristive memory |
0.3 | 1 | 2018 | Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Memory systems
non-volatile memory |
0.3 | 1 | 2018 | Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Energy-efficient computing
low-power design |
0.1 | 1 | 2018 | Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Electronic design automation › logic synthesis › logic minimization
boolean function minimization |
0.0 | 1 | 1972 | Clause-Column Table Approach for Generating All the Prime Implicants of Switching Functions · IEEE Trans. Computers 1972 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1972 | Clause-Column Table Approach for Generating All the Prime Implicants of Switching Functions · IEEE Trans. Computers 1972 |
Electronic design automation › logic synthesis
prime implicant generation |
0.0 | 1 | 1972 | Clause-Column Table Approach for Generating All the Prime Implicants of Switching Functions · IEEE Trans. Computers 1972 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.3boolean algebra · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | Memristor-Based High-Speed Memory Cell With Stable Successive Read OperationabstractThe memristor-based memory cell design is getting renewed attention in recent years due to its high speed and low power consumption. This paper aims at designing a novel hybrid memory cell incorporating a minimum number of transistors for a rapid bidirectional write operation. The read stability is one of the key elements for high efficiency and superior performance in memory. The memory cell in this paper was designed undertaking adequate measures for maintaining the stability in successive reads without any refresh operation. Extensive simulation experiments were conducted using 32-nm predictive technology model transistors and the results demonstrate superb performance and sound stability of the proposed memory cell in terms of read/write time as well as switching power consumptions. Mohammad Nazmus Sakib, Rakibul Hassan, Satyendra Biswas, Sunil R. Das |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 4 |
| 2004 | Implementation of Embedded Cores-Based Digital Devices in JBits Java Simulation Environment
Mansour H. Assaf, Rami S. Abielmona, Payam Abolghasem, Sunil R. Das, Emil M. Petriu, Voicu Groza, Mehmet Sahinoglu |
CIT | 4 |
| 1997 | Delay Fault Coverage Enhancement Using Variable Observation Times
Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das |
J. Electron. Test. | 3 |
| 1995 | On testing of sequential machines using circuit decomposition and stochastic modelingabstractTest generation for sequential circuits has been a difficult task. This is due to the large search space to be considered in test pattern generation. In this paper the detection of permanent faults in sequential circuits by random testing is analyzed utilizing the circuit partitioning approach together with a continuous parameter Markov model. Given a large sequential circuit, it is partitioned into several smaller partitions using either series or parallel decomposition. For each partition with certain stuck faults specified, the original state table and its error version are derived from an analysis of the partition under fault-free and faulty conditions, respectively. A random testing strategy that uses a three-state Markov model is used for detecting permanent stuck faults. Experimentation on various sequential circuits has shown that a significant saving in testing or test generation time can be achieved if we partition the circuit and then test each of its components as opposed to testing the circuit in its original form.> Sunil R. Das, Wen-Ben Jone, Amiya Nayak, Ian Choi |
IEEE Trans. Syst. Man Cybern. | 1 |
| 1995 | CACOP-a random pattern testability analyzerabstractIn this paper a new method called CACOP For the detection probability analyses of random test patterns is proposed. Considering computational complexity, CACOP is a compromise between O(n/sup 2/) testability analyses like full-range cutting algorithm (FRCA) and linear time testability analyses like the controllability observability program (COP). By propagating bounds of controllabilities and observabilities, CACOP can determine the detection probability lower bound (DPLB) efficiently. The DPLBs derived by CACOP are potentially higher (and thus more accurate) than by FRCA; in addition, CACOP is computationally more efficient than FRCA. The conventional linear time testability analyses cannot guarantee the derivation of DPLBs. On the contrary, CACOP can achieve the goal with tolerable increase in computing complexity.> Wen-Ben Jone, Sunil R. Das |
IEEE Trans. Syst. Man Cybern. | 2 |
| 1994 | Designing General-Purpose Fault-Tolerant Distributed Systems - A Layered ApproachabstractGeneral-purpose distributed systems comprised of computing nodes with different characteristics and connected by high-speed communication networks are very popular these days. The development of a dependable distributed system, however, necessitates the use of various techniques including fault tolerance to avert occurrences of failures or system malfunction. The ad hoc techniques of adding redundancy to improve reliability are not always suitable in these circumstances because of excessive design cost. Redundancies have to be allocated at various hardware and software levels in order to optimize their utilization in the system. This paper considers the design of general-purpose fault-tolerant distributed systems based on a layered approach. The benefits of the layered approach in the process of allocation of redundancy and fault tolerance at various system levels are presented and analyzed in the paper. Amiya Nayak, Wen-Ben Jone, Sunil R. Das |
ICPADS | 3 |
| 1992 | On random testing for combinational circuits with a high measure of confidenceabstractOne of the most important problems in random testing is the measurement of test confidence after a sequence of test vectors has been applied. Sequential statistical analysis is employed to determine the random test confidence. According to the analysis, the random test confidence depends on the detection probability of the circuit under test, the random test length, and the manufacturing yield. A detection procedure driven by a test quality indicator without presumed random test length is proposed based on the results of the sequential statistical analysis. Performance evaluation and simulation results demonstrate that the sequential statistical analysis reflects a better random test confidence than conventional approaches. This difference is due to the fact that conventional test confidence measures do not take the manufacturing yield into account.> Sunil R. Das, Wen-Ben Jone |
IEEE Trans. Syst. Man Cybern. | 1 |
| 1990 | Multiple-output parity bit signature for exhaustive testing
Wen-Ben Jone, Sunil R. Das |
J. Electron. Test. | 2 |
| 1990 | Probabilistic modeling and fault analysis in sequential logic using computer simulationabstractThe problem of detecting permanent faults in sequential circuits by random testing is analyzed utilizing a continuous parameter Markov model. Given a sequential circuit with certain stuck faults specified, the original state table and its error version can be readily derived from an analysis of the circuit under fault-free and faulty conditions, respectively. By simulation of these two tables on a computer, the parameters of the desired Markov model can be obtained. The approach does not require formulation of a product state table corresponding to the fault-free state table and its faulty version, which is rather difficult, when dealing with large circuits. For a specified confidence degree, it is easy to derive the parameters of the model and to calculate the required lengths of random test patterns or the maximum testing time. A complete mathematical analysis of the model is given. It provides insight into the nature of faults in relation to random testing and the associated confidence degree.> Sunil R. Das, Wen-Ben Jone, K. L. Wong |
IEEE Trans. Syst. Man Cybern. | 1 |
| 1979 | Transition matrices in the measurement and control of synchronous sequential machines
Sunil R. Das, C. L. Sheng, Zen Chen, W. J. Hsu |
Inf. Sci. | 1 |
| 1978 | Strong connectivity in symmetric graphs and generation of maximal minimally strongly connected subgraphs
Sunil R. Das, C. L. Sheng |
Inf. Sci. | 1 |
| 1973 | Multiform Partial Symmetry and LinearityabstractIt is known from a paper by Das that multiform total symmetry is equivalent to linearity. In this correspondence the results of Das are generalized and a simple proof is given to show that even for multiform partial symmetries the corresponding subfunctions are linear subfunctions. N. S. Khabra, Sunil R. Das |
IEEE Trans. Computers | 2 |
| 1972 | Clause-Column Table Approach for Generating All the Prime Implicants of Switching FunctionsabstractThis note describes an iterative procedure for generating the prime implicants of switching functions by utilizing a new tabular mode of functional representation called clause-column table. The procedure generates all the prime implicants and can be applied equally well to functions given in the sum-of-products or in the product-of-sums froms, both canonical and noncanonical. The procedure can also be readily adapted to determine the prime implicants of functions having a large number of unspecified or DON'T CARE terms. Sunil R. Das, N. S. Khabra |
IEEE Trans. Computers | 1 |