Jie Ying, Zihong Chen, Zhefan Wang, Wanli Jiang, Chenyang Wang, Zhonghang Yuan, Haoyang Su, Huanjun Kong, Fan Yang, Nanqing Dong. Proceedings of the 63rd Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers). 2025.

Prioritizing or reweighting important samples has been recognized as an effective means of improving the efficiency of deep-reinforcement learning (DRL) algorithms. However, many existing techniques encounter stability challenges, limiting efficiency and increasing computational costs and training time. In this study, we aim to improve training efficiency by exploring the intrinsic relationship between sample efficiency and stability. To achieve this, we propose the Stability Contribution Index (SI), which assigns sample priorities based on their impact on stability and employs them to weight the value loss, thereby promoting stable learning and improving efficiency. The effectiveness of our method is validated through comprehensive experiments on two distinct benchmarks: 1) the continuous control domain DMControl and 2) the discrete control environment ProcGen. Compatible with both off-policy and on-policy DRL algorithms, our approach significantly improves sample efficiency and overall performance by fostering greater stability during training. Additionally, experimental results show that our method outperforms well-established sample-efficient reinforcement learning techniques across multiple settings.

Achieving robust and real-time 3D perception is fundamental for autonomous vehicles. While most existing 3D perception methods prioritize detection accuracy, they often overlook critical aspects such as computational efficiency, onboard chip deployment friendliness, resilience to sensor mounting deviations, and adaptability to various vehicle types. To address these challenges, we present NVAutoNet: a specialized Bird’s-Eye-View (BEV) perception network tailored explicitly for automated vehicles. NVAutoNet takes synchronized camera images as input and predicts 3D signals like obstacles, freespaces, and parking spaces. The core of NVAutoNet’s architecture (image and BEV backbones) relies on efficient convolutional networks, optimized for high performance using TensorRT. Our image-to-BEV transformation employs simple linear layers and BEV lookup tables, ensuring rapid inference speed. Trained on an extensive proprietary dataset, NVAutoNet consistently achieves elevated perception accuracy, operating remarkably at 53 frames per second on the NVIDIA DRIVE Orin SoC. Notably, NVAutoNet demonstrates resilience to sensor mounting deviations arising from diverse car models. Moreover, NVAutoNet excels in adapting to varied vehicle types, facilitated by inexpensive model fine-tuning procedures that expedite compatibility adjustments.

It's been a long history that most object detection methods obtain objects by using the non-maximum suppression (NMS) and its improved versions like Soft-NMS to remove redundant bounding boxes. We challenge those NMS-based methods from three aspects: 1) The bounding box with highest confidence value may not be the true positive having the biggest overlap with the ground-truth box. 2) Not only suppression is required for redundant boxes, but also confidence enhancement is needed for those true positives. 3) Sorting candidate boxes by confidence values is not necessary so that full parallelism is achievable. In this paper, inspired by belief propagation (BP), we propose the Confidence Propagation Cluster (CP-Cluster) to replace NMS-based methods, which is fully parallelizable as well as better in accuracy. In CP-Cluster, we borrow the message passing mechanism from BP to penalize redundant boxes and enhance true positives simultaneously in an iterative way until convergence. We verified the effectiveness of CP-Cluster by applying it to various mainstream detectors such as FasterRCNN, SSD, FCOS, YOLOv3, YOLOv5, Centernet etc. Experiments on MS COCO show that our plug and play method, without retraining detectors, is able to steadily improve average mAP of all those state-of-the-art models with a clear margin from 0.3 to 1.9 respectively when compared with NMS-based methods.

Energy Consumption Ratio (ECR) test, a current-based test, has shown its ability to reduce the impact of process variations and detect hard-to-detect faults. The effectiveness of ECR tests may be degraded by a large number of normal transitions in a circuit, which may bury the fault impact on the overall current. For deterministic ECRs, the fault-oriented ECR tests are generated with an algorithm to minimize the number of normal transitions not related with the sensitizable path of the target faults. For generalized ECRs, however, the test patterns are generic without targeting any specific faults and therefore may cause a significant amount of transient activities in a CUT. This issue is addressed in this paper by utilizing a DFT technique, multiple scan chain design. This technique virtually partitions the circuit into several sections, so that the transitions in each section can be much less compared with those in the whole circuit. The fault impact can be more significant with fewer transitions in the circuit, which hence increases the ECR test effectiveness. The anti-process-variation property of the ECR metric is also demonstrated through a negligible lotto-lot shift. Finally, the effectiveness of ECR tests with different thresholds is compared with existing traditional tests. 1

Very-Low-Voltage, Ultra-Low-Voltage (a modified version of Minimum-Voltage), and Energy Consumption Ratio (a recently developed test metric) tests are applied as supplemental tests along with existing traditional tests to a biomedical IC product. The effectiveness and efficiency of these supplemental tests are evaluated and compared with some major traditional tests. The effectiveness analysis indicates that Ultra-Low-Voltage and Energy Consumption Ratio tests identified potentially defective devices from good devices. The efficiency analysis shows that the Energy Consumption Ratio test is much more efficient than Very-Low-Voltage, Ultra-Low-Voltage and major traditional tests.

Dynamic I/sub dd/ techniques can potentially address the limitations of traditional test techniques and the Idd, test. Normal process variations in manufacturing affect dynamic Idd techniques in two ways. Since a fault-free circuit can produce a range of responses, they necessitate the use of a threshold-based test process. Process variations also degrade the resolution and consequently the fault coverage of a test technique. The authors develop statistical techniques to set thresholds in a dynamic Idd test process. The techniques use Principal Component Analysis, a statistical analysis technique,. to identify process corners and compute statistical models. Our techniques are applied to average current-based dynamic tests and to tests based on the energy consumption ratio (ECR). The ECR is a new test metric which offers several advantages, including tolerance to process variations, over other dynamic test techniques. The authors demonstrate that their techniques lead to computationally efficient methods to set accurate thresholds without either significant yield or fault coverage loss. To the best of their knowledge, this is the first systematic technique to set thresholds for a dynamic I/sub dd/ test method.

Dynamic I/sub dd/ test techniques are obtaining more attention from both academia and industry, because of their ability to further improve product quality beyond tests based primarily on I/sub ddq/ test and other traditional test techniques. Normal process variations in wafer fabrication decrease the defect coverage and affect the application of dynamic I/sub dd/ test techniques. Energy Consumption Ratio (ECR) test, a recent test metric based on dynamic currents, shows its tolerance to process variations, over other dynamic test techniques. We investigate this technique as a method of providing additional test coverage to production wafers that were fabricated using two different planarization technologies. One set was fabricated with a Spin-on-Glass (SOG) planarization technology, and the other set with Chemical Mechanical Polishing (CMP). The SOG wafers used in our experiments contain defects known as "poisoned vias." We show that the ECR is effective in detecting defects of this type where other traditional test methods are not.

As tester complexity and cost increase, reducing test time is an important manufacturing priority. Test time can be reduced by ordering tests so as to fail defective units early in the test process. Algorithms to order tests that guarantee optimality require execution time that is exponential in the number of tests applied. We develop a simple polynomial-time heuristic to order tests. The heuristic, based on criteria that offer local optimality, offers globally optimal solutions in many cases. An ordering algorithm requires information on the ability of tests to detect defective units. One way to obtain this information is by simulation. We obtain it by applying all possible tests to a small subset of manufactured units and assuming the information obtained from this subset is representative. The ordering heuristic was applied to manufactured digital and analog integrated circuits (ICs) tested with commercial testers. When both approaches work, the orders generated by the heuristic are optimal. More importantly, the heuristic is able to generate an improved order for large problem sizes when the optimal algorithm is not able to do so. The new test orders result in a significant reduction, as high as a factor of four, in the time needed to identify defective units. We also assess the validity of using such sampling techniques to order tests.

Dynamic current-based test techniques can potentially address the drawbacks of traditional and I/sub ddq/ test methodologies. The quality of dynamic current-based test is degraded by process variations in integrated circuit (IC) manufacture. The energy consumption ratio (ECR) is a new metric that improves the effectiveness of dynamic current test by reducing the impact of process variations by an order of magnitude. In this paper, we address issues that are of practical importance to an ECR-based test methodology. We use the ECR to test a low-voltage submicron IC with a microprocessor core. The ECR more than doubles the effectiveness of the dynamic current test already used to test the IC. The defect coverage of the ECR is greater than that offered by any other test, including I/sub ddq/. We develop a logic-level fault simulation tool for the ECR. We also show that statistical techniques can be used to set thresholds for an ECR-based test process. Our results demonstrate that the ECR offers several advantages relative to other transient current-based test methods and to I/sub ddq/ test. The ECR offers the potential to be a high quality low cost test methodology.

Dynamic-current based test techniques can potentially address the drawbacks of traditional and I ddq test methodologies.The quality of dynamic current based test is degraded by process variations in IC manufacture.The energy consumption ratio (ECR) is a new metric that improves the effectiveness of dynamic current test by reducing the impact of process variations by an order of magnitude.We address several issues of significant practical importance to an ECR-based test methodology.We use the ECR to test a low-voltage submicron IC with a microprocessor core.The ECR more than doubles the effectiveness of the dynamic current test already used to test the IC.The fault coverage of the ECR is greater than that offered by any other test, including I ddq .We develop a logic-level fault simulation tool for the ECR and techniques to set the threshold for an ECR-based test process.Our results demonstrate that the ECR offers the potential to be a high-quality low-cost test methodology.To the best of our knowledge, this is the first dynamic-current based test technique to be validated with manufactured ICs.

Process variations degrade the resolution and consequently the fault coverage of I/sub dd/ test techniques. We develop statistical techniques to set thresholds in a dynamic I/sub dd/ test process. The techniques use principal component analysis to identify process corners and compute statistical models. Our techniques are applied to average current-based dynamic test and to test based on the energy consumption ratio. We demonstrate that our techniques lead to computationally efficient methods to set accurate thresholds without either significant yield or fault coverage loss. To the best of our knowledge, this is the first systematic technique to set thresholds for a dynamic I/sub dd/ test method.

Test time can be reduced by ordering tests so as to fail defective units early in the test process. An ordering algorithm requires information on the ability of tests to detect defective units. We obtain it by applying all possible tests to a small subset of manufactured units and assume the information obtained from this sub-set is representative. We develop a simple polynomial-time heuristic which uses the information from the sample set to order tests. The heuristic, based on criteria that offer local optimality, offers globally optimal solutions in many cases. Optimal test ordering algorithms require execution time which is exponential in the number of tests applied. In our experiments, the heuristic results in a significant reduction in test time for manufactured digital and analog ICs.

Unique input/output(UIO) sequences are used for state verification and functional test in finite state machines. A UIO sequence for a state s distinguishes it from other states in the FSM. Current algorithms to compute UIO sequences are limited in their applicability to FSMs with binary input symbols such as those found in con trol applications. Execution times of traditional approaches are exponential in the n umber of FSM inputs. We dev elop a new heuristic algorithm to generate UIO sequences for FSMs with binary inputs. Execution time is reduced significantly b y reducing the size of the search space. When a UIO sequence cannot be generated, our algorithm generates a small n umber of functional faults for state verification.

We develop a new technique for fault detection based on a new metric, the energy consumption ratio (ECR). ECR-based test can detect faults, such as redundant faults, that escape detection with other techniques. Though the ECR is a metric based on the supply current, an analog parameter, it is remarkably tolerant to the impact of process variations. The quality of ECR-based test is demonstrated through extensive simulation on a process offered by MOSIS. We also present a test generation algorithm for the new test technique. When applied to benchmark circuits, this technique reliably detects a large fraction of the combinationally redundant faults in them.