This paper presents a DFT-IDFT-based minimum-segment calibration technique for SAR ADCs, specifically targeting capacitor mismatch-induced nonlinearity under incoherent sampling conditions. By employing multi-term cosine-sum window functions, spectral leakage is significantly suppressed, enabling accurate digital estimation of nonlinear bit-weight errors. The proposed method employs lookup tables (LUTs) to integrate DFT/IDFT and windows, greatly simplifying ADC error extraction, while employingLDL${}^{\mathbf {T}}$decomposition for numerically stable least-squares estimation. A novel metric, Maximum Single-Tone Offset Attenuation (MSTOA), is introduced to evaluate window functions’ efficacy in suppressing spectral leakage. Among digital calibration methods, the minimum-segment approach achieves substantial improvement in calibration accuracy while maintaining comparable computational complexity. The non-iterative, one-shot error extraction method eliminates convergence delays inherent in iteration-based methods. Additionally, built-in self-test (BIST) capability enables concurrent dynamic performance evaluation. Measurement results from a 20-bit 1-MS/s prototype implemented in 180-nm CMOS demonstrate that post-calibration SNDR/SFDR can be improved by 22.7dB and 27.3 dB, respectively.

This brief presents a successive approximation register (SAR)-assisted noise-shaping (NS) pipelined analog-to-digital converter (ADC) with the reusing feedback capacitor (RFC) technique. With the proposed RFC technique, the feedback capacitor can simultaneously accomplish the 1st-stage residue transfer, the 2nd-stage quantization error extraction and feedback, and reference voltage matching, which reduces circuit complexity and enhances linearity. To mitigate the noise leakage resulting from gain error, a single-stage closed-loop gain-boosted cascoded floating inverter amplifier (GBCFIA) with 85-dB open-loop gain is proposed. The GBCFIA demonstrates a combination of robustness, high accuracy, and enhanced energy efficiency. Fabricated in a 65-nm CMOS process, the ADC prototype achieves a measured 78.5-dB signal-to-noise and distortion ratio (SNDR) in a 250 MS/s at an oversampling ratio (OSR) of 8. With 2.96-mW power consumption, it achieves an SNDR-based Schreier figure of merit (FoM) of 175.7 dB.

This paper presents a fully integrated reconfigurable single-channel IC with high energy efficiency for bio-signal acquisition in Internet-of-Medical Things (IoMT) systems. The overall signal chain consists of a capacitively-coupled instrumentation amplifier (CCIA) and a 16-bit delta-sigma ($\Delta$$\Sigma$) ADC. The ADC is directly driven by the CCIA without a traditional driver stage. The folded path of the first stage in CCIA is sliced for reconfigurable noise levels. In addition, a single-stage floating inverter amplifier (FIA) assisted by the correlated-level-shifting (CLS) technique is employed in the switched-capacitor (SC)$\Delta$$\Sigma$modulator for fully dynamic operation with sufficient DC gain. Fabricated in 180-nm CMOS, the CCIA achieves an input-referred noise level ranging from 35.8 to 67 nV/$\surd$Hz with a best noise-efficiency factor (NEF) of 5.54. It corresponds to an integrated noise ranging from 0.63 to 1.16$\mu$$\text{V}_\text{rms}$(0.5-100 Hz) and 1.93 to 3.51$\mu$$\text{V}_\text{rms}$(0.1-3 kHz), respectively. The ADC achieves a peak SNDR of 92.6 dB for a 2.3-$\text{V}_\text{pp}$differential input and can support 16$\times$power/BW reconfigurability with ENOB$>$15 bit. The complete system occupies an active area of 0.56 mm$^{2}$and achieves 85.7-dB system SNDR over a 500 Hz BW with an OSR of 128. It consumes 36.8$\mu$W from a 1.8-V supply, corresponding to an SNDR-based Schreier FoM of 157 dB. Biological measurement is demonstrated successfully, and the results verify that the proposed IC is applicable to high-quality ExG signal acquisition.

This brief presents a ping-pong continuous-time noise-shaping successive-approximation register (CT NS-SAR) analog-to-digital converter (ADC) architecture. Compared with the previous works, two ping-pong operation DACs are utilized to release the conversion time from 5% to 95% of the clock period, while ensuring the continuity of CT integration in the time domain, thus realizing the ideal noise transfer function (NTF) of the true CT-NS SAR. The DAC of each channel performs two roles of integration and conversion alternately, not only converting the signal in the current period but also bringing the generated residue voltage into the next period. Besides, the$G_{ {m}}$-OTA-Cintegrator replaces the open-loop$G_{ {m}}$-Cintegrator, where the OTA isolates the output parasitic capacitance, achieving an exact CT integration. The effective conversion bits are calculated by the bandwidth (BW) and the time of bit cycle, thus avoiding the redundant bits. Verified by postsimulation in a 65-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB over 20-MHz BW with an oversampling ratio (OSR) of 15. Under a 1.2-V supply voltage, the ADC consumes 2.3 mW and exhibits a Schreier figure of merit (FoM${}_{ {S}}$) of 170.2 dB.

This article presents a fully dynamic switched-capacitor zoom ADC with 1st-order interstage leakage shaping (ILS). Noise shaping capability is integrated into the coarse stage by a low-cost error-feedback (EF) path, effectively mitigating quantization noise leakage in the traditional zoom architecture due to the non-unity STF. In addition, a swing-enhanced floating inverter amplifier (FIA) architecture is proposed for improved linearity as well as fully dynamic operations. The prototype ADC is fabricated in a 65-nm CMOS process and occupies an active area of 0.22 mm2. With a 1.2-V supply, it achieves 98.1-dB peak SNDR over a 20-kHz bandwidth with 142.8$\mu $W power consumption, resulting in a DR-based Schreier FoM of 182.9 dB and an SNDR-based FoM of 179.5 dB, respectively. According to the measurement results, 8$\times $power/BW configurability can be achieved by the zoom ADC while maintaining SNDR above 98 dB.

This article presents a single-loop third-order discrete-time delta-sigma modulator (DTDSM) with a 4-bit second-order noise shaping successive approximation register (NS SAR) quantizer. To realize an aggressive noise transfer function (NTF), a novel Finite Impulse Response (FIR) filter is embedded in the NS SAR. As employing a flipped voltage follower (FVF), which offers unity gain instead of an open loop dynamic amplifier, the proposed FIR filter is sharp and insensitive to process, voltage, and temperature (PVT) variation. Fabricated in a 65-nm 1P9M CMOS technology, the prototype DTDSM consumes$44 \mu \text{W}$when operating at a 1.2-V supply voltage and a sampling rate of 2.4 MS/s. It achieves a peak Schreier figure of merit (FoM) of 177.9 dB with a signal-to-noise and distortion-ratio (SNDR) of 91.3 dB at an oversampling ratio (OSR) of 64.