Spiking Neural Networks (SNN) is well-suited for always-on near-sensor intelligence, due to its spike-driven nature; however, its IC realization is complicated by the temporal dimension. Asynchronous low-power SNN chips employing analog computing-in-memory (CIM) techniques have been demonstrated to enable real-time, energy-efficient inference. However, their tolerance to nonidealities remains to be improved, and their peripherals for multiphase or multilevel signal control are complex. This paper proposes a general-purpose, spike-driven SNN chip designed with efficient analog-computing circuits, featuring two key contributions: 1) A compact direct current-add CIM synapse design that significantly simplifies control peripherals, thereby reducing latency and enhancing energy efficiency. 2) A PVT-aware multi-network learning method underpinned by detailed analyses and modeling, coupled with a label-normalization-based synapse-strengthening method, to mitigate the impact of nonidealities. Fabricated in 65nm CMOS process, the proposed design achieves a state-of-the-art latency of$10\mu $s and an energy efficiency of 0.40pJ/spike. The generalization ability of the design is verified through its successful application to two distinct tasks: voice activity detection (VAD) and ECG anomaly detection. The tolerance to nonidealities is validated by the VAD task. The ten chips maintain over 90% detection accuracy across signal-to-noise ratios (SNRs) of$4\sim 16$dB, ±10% supply voltage variation, and a temperature range of$- 25\sim 55^{\circ }$C.

Piezoelectric energy harvesting interfaces are mainly categorized into single-stage conversion interfaces with high efficiency and cascaded conversion interfaces with high output power. However, the single-stage conversion interface has limited output power and lacks an MPPT configuration, while the cascaded conversion interface suffers from low end-to-end harvesting efficiency due to the cascaded conversion process. This paper proposes a load-independent Split-S-SSHI (SS-SSHI) interface with an envelope-tracking MPPT that can simultaneously achieve high output power and high end-to-end efficiency. In addition, the split S-SSHI eliminates the need for a rectifier capacitor and enhances the response speed of the MPPT. The proposed harvester is fabricated in a 0.18-$\mu $m CMOS process with a low quiescent current of 39 nA. Measurements indicate a maximum MPPT efficiency and end-to-end harvesting efficiency up to 99.5% and 91.9%, respectively, and the maximum output power reaches 9.7 times that of a conventional full-bridge rectifier.

Conventional duty-cycle-based (DCB) maximum power point tracking (MPPT) schemes generally assume a 50% duty cycle for operation at the maximum power point (MPP). However, due to nonideal losses in the piezoelectric transducer (PZT), such as dielectric loss, mechanical damping, and rectifieroff-state leakage, the actual optimal duty cycle deviates from this nominal value. This brief develops a theoretical model that incorporates these losses, which is derived, analyzed, and experimentally validated using a piezoelectric energy harvester (PEH) integrated with a bias-flip MPPT regulating rectifier (BMRR). Measurement results show that the optimal duty cycle ranges from 42.3% to 42.8%, under which the rectifier delivers 1.1 times the output power compared to operation at a fixed 50% duty cycle. Furthermore, the proposed rectifier achieves a peak power conversion efficiency (PCE) of 89.6% and demonstrates a 7.4-fold improvement in energy extraction compared to a full-bridge rectifier (FBR).

This work presents a self-feeding-priority power management strategy for a multi-input piezoelectric energy harvester based on the synchronous electric charge extraction (SECE). While conventional SECE can harvest intermittent vibration energy, it typically relies on battery power, which is continuously drained during vibration-free periods, causing net energy loss. The proposed solution prioritizes using harvested energy to sustain harvester operation, with surplus directed to storage, preventing consumption of stored energy when environmental kinetic energy is absent. In addition, by integrating a voltage clamping circuit and multistep charge extraction, the harvester efficiently harvests energy from diverse kinetic energy, operating over a wide input range. Fabricated in 180 nm CMOS technology, the harvester supports autonomous cold-start from 0.35 V and reliably harvests energy from periodic, shock, plucking, pressing, and walking-induced vibrations.

This article presents a low-power bandgap reference (BGR) featuring high power supply rejection ratio (PSRR) and fast start-up capability, operating across a wide supply voltage range of 1.3–5 V. A novel prebiased pulse current injection technique is proposed in the start-up circuit, achieving a 1% settling time of$50~\mu $s and a$25\times $speed gain during start-up. To enhance supply noise immunity, the proposed BGR employs a preregulated (PR)-based amplifier that effectively decouples the reference voltage from supply voltage fluctuations. Fabricated in a 0.18-$\mu $m BCD process, the proposed reference occupies an active area of 0.0394 mm2. Under a 5 V supply, the circuit generates a 1.2 V reference voltage while consuming only 48 nA quiescent current. Operating down to a minimum supply voltage of 1.3 V, it maintains a low power consumption of 57.2 nW at room temperature. The reference exhibits an average temperature coefficient (TC) of 5.95 ppm/°C across a wide temperature range ($- 40~^{\circ }$C to$125~^{\circ }$C) and achieves an outstanding line sensitivity (LS) of 0.00308%/V over the 1.3–5 V supply range. Furthermore, the measured PSRR reaches −85 dB at 100 Hz.

In this paper, a mutually synergistic hybrid energy harvesting (SHEH) circuit with both AC and DC energy harvesting capability is proposed. Within the proposed hybrid harvester, the vibration period of the piezoelectric transducer (PZT) is served as the switching signal for photovoltaic (PV) energy harvesting so that a dedicated clock generator is saved. Meanwhile, during the sampling phase, a small portion of the PV energy is injected into the PZT as an investment, which enhances the damping force and charge extraction of the PZT. Theoretically, the total synergistically extracted power from the proposed hybrid harvester is more than the sum of the power obtained from each transducer independently. The proposed SHEH circuit is fabricated with a 0.18-$\mu \text{m}$CMOS process. The buck-boost converter with zero-current switching control achieves a peak efficiency of 82.8%, and the maximum efficiency of piezoelectric energy harvesting can reach 4.5 times that of the full-bridge rectifier.

Using coaxial through-silicon technologies, a new 3-D capacitor integrated on a silicon interposer is proposed. The capacitance of coaxial through silicon via (CTSV) capacitors is extracted, analyzed, and compared. The results obtained from the analytical model and the finite-element method exhibit good agreement with various design parameters, and the error between the proposed model and measurement remains less than 7.41%. Due to high capacitance density up to 22.4 nF/mm2, the 3-D capacitor is adopted as a decoupling capacitor for the on-chip low-dropout (LDO) regulator design. The proposed LDO is developed in a 180-nm CMOS technology and shows unique advantages regarding the power supply rejection (PSR) performance, quiescent current, and area compared with that of the conventional LDOs with off-chip capacitors and capacitor-less (CL) LDOs.

This paper models and studies silicon-core coaxial through silicon vias (CTSVs), in which the metal via is replaced with a Cu coated silicon pole. Based on the physical structure of CTSVs, the impact of various design parameters on the electrical performance is investigated. It is shown that the high frequency loss of CTSVs is dominated by the dielectric and the increase in the thickness of plated Cu decreases the CTSV insertion loss. Furthermore, a set of analytical formulas are presented to capture the equivalent resistance-inductance-capacitance-conductance (RLCG) parameters of CTSVs, it yields accuracy results comparable to those with a commercial full-wave simulator. Finally, a comparison of the proposed CTSVs with other two TSV structures is carried out to demonstrate the feasibility of the silicon-core CTSVs in future three-dimensional (3D) integration.

For standard loess sections in the Chinese Loess Plateau (CLP), paleosols always have higher magnetic susceptibility (MS) than adjacent loesses. But this characteristic is not always suitable to MS records in loess-paleosol sequences from Central Asia. Here we report MS results of two loess sections in Yili basin, Central Asia. The MS variation of one loess section with an elevation of 1432m is identical with that of loess-paleosol sequences in the CLP, but the other one at 875m have opposite trend. Based on field investigation, pedogenesis characteristics observations, carbonate, lithological and grain-size correlations, the authors suggest that the differences of regional paeloprecipitation related to altitudes during last interglacial period between the two sections are responsible for their differences of MS. Carbonate deposits also have influence on decrease MS. The susceptibility enhancement of pedogenesis model for loess-paleosol sequences in the CLP can not interpret completely the MS variations of loess sections from Central Asia area. It should be careful to reconstruct paleoclimatic change using susceptibility as a proxy in Central Asia area.