Field programmable gate arrays (FPGAs) are designed and fabricated using the most advanced CMOS technology nodes to meet performance and power demands. This makes them susceptible to many manufacturing and reliability challenges. Increasing chip temperature is a major reliability concern since various failure mechanisms are accelerated at high chip temperature, which require thermal-aware testing to detect them. External devices like thermal chambers are usually used to heat up the chip to a desired temperature in order to apply the test. However, there are many limitations for these external devices, which make the thermal-aware testing of the FPGA a challenging process. In this paper, thermal-aware testing of FPGAs using built-in self-heating is presented, in which the internal resources of FPGA are used to build controlled self-heating elements (SHEs). These controlled SHEs are distributed across the FPGA and integrated with the test scheme to generate the required temperature profile for testing, and thus no external devices for heating up the FPGA are needed. We present two different categories of SHEs integration techniques for different testing purposes. The first one is for built-in self-test, and the second one is for application-dependent testing. The techniques are applied on representative test cases. The experimental results show that a wide range of maximum chip temperatures can be achieved (from 50 °C up to 125 °C on Virtex-5 FPGA) with a high accuracy (±1 °C).

Modern Field Programmable Gate Arrays (FPGAs) are built using the most advanced technology nodes to meet performance and power demands. This makes them susceptible to various reliability challenges at nano-scale, and in particular to transistor aging. In this paper, an experimental analysis is made to identify the main parameters and phenomena influencing the performance degradation of FPGAs. For that purpose, a set of controlled ring-oscillator-based sensors with different frequencies and tunable activity control are implemented on a Spartan-6 FPGA. Thus, the internal switching activities (SAs) and signal probabilities (SPs) of the sensors can be varied. We performed accelerated-lifetime conditions using elevated temperatures and voltages in a controlled setting to stress the FPGA. A novel monitoring method based on measuring the electromagnetic emissions of the FPGA is used to accurately monitor the performance of the sensors before and after the stress. The experiments reveal the extent of performance degradations, the impact of SPs and SAs, and the relative impacts of BTI and HCI aging factors.

Field Programmable Gate Arrays (FPGAs) are designed and fabricated using the most advanced CMOS technology nodes to meet performance and power demands. This makes them susceptible to many manufacturing and reliability challenges. Increasing chip temperature is a major reliability concern since various failure mechanisms are accelerated at high chip temperature, which require thermal-aware testing to detect them. External devices like thermal chambers are usually used to heat up the chip to a desired temperature in order to apply the test. However, there are many limitations for these external devices, which make the thermal-aware testing of the FPGA a challenging process. In this paper, a self-heating approach for thermal-aware testing of FPGAs is presented, in which the internal resources of FPGA are used to build controlled self-heating elements (SHEs). These controlled SHEs are distributed across the FPGA and integrated with the built-in self-test (BIST) scheme to generate the required temperature profile for testing. Thus, no external devices for heating up the FPGA are needed. The experimental results show that a wide range of maximum chip temperatures can be achieved (from 50°C up to 125°C on Virtex-5 FPGA) with a high accuracy (±1°C).

Accurate thermal profile estimation for FPGA, at design time, is necessary to avoid unexpected thermal hot-spots in the circuit before deploying the FPGA to the in-field operation. Both accurate dynamic and leakage power values are needed for the thermal profile estimation and they can be estimated using the FPGA vendor's tools. However these report leakage power as a single value for the whole chip, and no details are given in literature or the FPGA toolset about its distribution across the FPGA chip for the thermal simulation. To cope with this problem, we present a method for properly distributing the leakage power across the FPGA chip. The method uses a temperature-leakage loop estimation model for distributing and adapting the leakage power for more accurate thermal simulation. Furthermore, to accurately calibrate the presented method and its model and also to validate the resulting thermal profiles, we utilize an infrared thermal camera, which measures the emissions from the backside of a Virtex-5 FPGA chip. The results of testing several designs, with different sizes and frequencies, show that our approach can achieve accurate thermal-profile estimation when compared to the camera measurements, with average absolute estimation error of around 1°C across the chip.

The continuous shrinking of CMOS transistors in the nano-scale era poses many manufacturing and reliability challenges such as process variation, sub-threshold leakage, power dissipation, increased circuit noise sensitivity, and reliability concerns due to transient (e.g. radiation-induced soft errors) and permanent (e.g. transistor aging) failures [1, 2]. State-of-the-art FPGAs, pushed by the ever-increasing demands on higher performance and lower power, use the latest advancements in CMOS technology [3, 4], and thus they share most of these challenges. Therefore, to guarantee the required lifetime of FPGA-mapped systems in the field, proper techniques at various levels should be devised. Transistor aging, as an important factor, causes an increase in the magnitude of threshold voltage, which in turn slows down the switching speed of the transistor and leads to timing failures and faster wear-out rates [5]. To properly deal with this issue in FPGAs, it requires modeling, monitoring and mitigation at device and architecture levels as well as the tool-chain at user level.

Bias Temperature Instability (BTI) plays a significant role in transistor aging. As the device dimensions shrink due to technology scaling, this problem poses serious reliability issues. Field Programmable Gate Arrays (FPGAs) use very advanced nano-scaled CMOS technologies, which makes them vulnerable to BTI-induced aging. Previous studies have analyzed the relationship between the configuration of Look-Up Tables (LUTs) and the input signal probabilities against BTI-induced aging of LUTs. In this paper, we propose two methods to mitigate BTI-induced aging in LUTs. The mitigation is performed by manipulating the configuration of the used LUTs and their input signal probabilities, while maintaining the functionality of the mapped design. We implemented the proposed methods using the academic tool Verilog to Routing (VTR). The experimental results show that our methods can mitigate BTI-induced aging of LUT substantially and improve the lifetime of the FPGA-mapped designs, on average, by more than 200%.

As the state-of-the-art FPGA devices use the latest advancements in CMOS technology, they also face the reliability challenges of nano-scale CMOS. Transistor aging, mainly due to Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI), is a major reliability issue. In this paper, we present a tool to predict the amount of aging-induced degradation for designs mapped to FPGA devices, to help the designers, in an early phase of the design flow, to choose the appropriate mapping and/or optimization efforts, in order to prolong the lifetime of their FPGA-mapped designs. The tool is based on system level abstractions for both BTI and HCI device level models, in addition to implicit device-level information existed in the power and timing reports provided from the FPGA's vendor tools. A case study of using the tool to explore different designs and mapping options shows that aging of the FPGA device is dependent on the design loaded onto it. Furthermore, different mappings and optimizations of the same circuit can result in different aging rates.

Transistor aging mostly due to Negative and Positive Bias Temperature Instability (NBTI and PBTI) is a major reliability threat for VLSI circuits fabricated in nanometer technology nodes. As much as FPGAs benefit from the most scaled and advanced technologies, they become more susceptible to transistor aging. In this paper, we investigate the effect of transistor aging on programmable routing resources of FPGAs, by considering different implementations through detailed SPICE simulations. The effects of different parameters, such as wire length, cascaded routing, routing fan-out, signal probability and supply voltage on the aging of routing resources are studied.

Transistor aging due to Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is a major reliability issue for aggressive device downscaling at nanoscale. State-of-the-art FPGA chips, which use most recent CMOS technologies and smallest feature sizes to meet high performance demands, are at the front line to face this problem. In this paper, we present the design and mapping of a low-cost logic level aging sensor for FPGA-based designs. The mapping of this sensor is designed to provide controlled sensitivity, ranging from a warning sensor to late transition detector. The functionality of the sensor has been verified on a Virtex5-based board. Area, delay, and power overhead of a set of sensors mapped for most aging-critical paths of representative designs are very modest. (≈ 1.3% area, ≈ 1.6% performance, and ≈ 1.5% power overhead).

Transistor aging mostly due to Negative and Positive Bias Temperature Instability (NBTI and PBTI) is a major reliability threat for VLSI circuits fabricated in nanometer technology nodes. These phenomena can shift the threshold voltage of transistor over time, increase their delays and cause timing failure and ultimately reduction of lifetime of VLSI chips. As much as FPGAs benefit from the most scaled and advanced technologies, they become susceptible to transistor aging. In this paper, we investigate the effect of transistor aging, due to NBTI and PBTI, in look-up tables (LUTs), by considering different implementations through detailed SPICE simulations. We found out that the delay degradation due to transistor aging depends on the mapped configuration, usage (input signal probability) as well as the specific LUT implementation. Moreover, the specific configuration mapped previously into an LUT has a considerable effect on the delay degradation of the currently used configuration of that LUT. We also found that the all-zero configuration which is normally used as the standby configuration is not the best choice and it may even result in high delay degradation.

This paper presents a general methodology for mapping a class of algorithms known as iterative algorithms to FPGA-based dynamically partially reconfigurable architectures in an adaptive and efficient manner. Hereby, each iteration step is mapped to a partial module on the FPGA, and modules can be added or removed to these connected modules on the FPGA dynamically using partial reconfiguration. The more modules and iteration steps, respectively, are concurrently executed on the FPGA, the higher the achieved through-put due to exploitation of pipelining in the design. Especially, numerical approximation algorithms allow a trade-off between precision of the final result and the execution time, and benefit by the proposed mapping methodology: When mapping an element of that class of algorithms to a partially dynamically reconfigurable platform, the number of modules can be increased or decreased at runtime depending on the desired quality of the results and the available area. Thus, the proposed general mapping methodology provides an acceleration of an important class of algorithms due to the execution in hardware, and allows at runtime a trade-off decision between execution time and quality of the results. Furthermore, a detailed description of an experimental implementation of a square root calculation on a reconfigurable platform is given as a prototype example to explain and show the benefits of the proposed approach.

Invasive computing is a novel paradigm for exploitation of run-time parallelism of future MPSoC architectures through resource-aware programming and dynamic reconfiguration of the underlying architectures. Based on the state and availability of resources, an invasive algorithm organizes its computation itself. This paper presents a general methodology for mapping invasive algorithms to FPGA-based dynamically reconfigurable architectures. A detailed description of a general invasive architecture on a reconfigurable platform is given. For 1D linear processor architectures, the applicability of this concept is tested and results show substantial flexibility gains with only marginal additional hardware cost.