This work presents two 4-bit resistor-string digital-to-analog converters (R-DAC) designed in 22nm FDSOI technology. Both DACs are connected to a shared resistor string to make the final layout more compact. The small on-resistance of the Transmission-Gate (TG) switches designed in the FDSOI node yields a low Internal non-linearity (INL) and Differential non-linearity (DNL) in the DACs output. The effect of the temperature variations on the linearity performance of the DACs is also studied. It is shown that the temperature gradients can be compensated for by equally distributing the switches on the layout area. Post-layout simulations show an approximately fixed INL and DNL of, respectively, 0. 17LSB and 0. 1LSB over a wide temperature range from -40°C to $125^{0} C$. Two R-DACs dissipate the static/dynamic power of 0. 12/0.155mW with the layout size of only 70 $\mu m^{2}$, showing a high performance for two 4-bit DACs.

The inefficiencies of von-Neumann computing architectures in performing high-level machine learning and neuromorphic operations have led to the need for new computational systems such as oscillatory neural networks, that are designed using emerging technologies. The frequency dynamics of Ferroelectric field-effect transistor (FeFET)-based coupled oscillator neurons, as integral parts of these novel computational networks are investigated in this paper. The concept of time to frequency modulation is also introduced which can be used to distinguish dynamical changes in the incoming signals. Simulation results show a significant reduction in power consumption with approximately 9 μW for each oscillator neuron. This is significant improvement over results reported for spin-torque and metal-insulator-migration oxide-based coupled-oscillators. Integrability with CMOS technology in conjunction with lower power consumption and simpler topologies make FeFET devices promising candidates for the next generation of neuromorphic computing platforms, and particularly for image, video, and audio processing tasks.

Degradation of power amplifier (PA), being a main part of a transceiver chain, affects the overall performance of a transceiver. This article reports, for the first time, an analytical reliability model of the hot-carrier injection (HCI) induced degradation in silicon-based PAs. HCI causes substrate current which is used to develop the proposed model. This model fits very well the simulation results of RelXpert, which is a well-established reliability simulation tool. This model predicts circuit degradation as a function of conduction angle and is valid for the different classes of PAs. With this model, a new approach for “reliability aware design” for PA design is developed and a tradeoff between PA performance and reliability is introduced.

This paper introduces a novel implementation of the low-power analog artificial neural network (ANN) using Multiple Input Floating Gate MOS (MIFGMOS) transistor for machine learning applications. The number of inputs to a neuron in an ANN is the major bottleneck in building a large scale analog system. The proposed MIFGMOS transistor enables to build a large scale system by combining multiple inputs in a single transistor with a small silicon footprint. Here, we show the MIFGMOS based implementation of the Extreme Learning Machine (ELM) architecture using the receptive field approach with transistor operating in the sub-threshold region. The MIFGMOS produces output current as a function of the weighted combination of the voltage applied to its gate terminals. In the ELM architecture, the weights between the input and the hidden layer are random and this allows exploiting the random device mismatch due to the fabrication process, for building Integrated Circuits (IC) based on ELM architecture. Thus, we use implicit random weights present due to device mismatch, and there is no need to store the input weights. We have verified our architecture using circuit simulations on regression and various classification problems such as on the MNIST data-set and a few UCI data-sets. The proposed MIFGMOS enables combining multiple inputs in a single transistor and will thus pave the way to build large scale deep learning neural networks.

We study, for the first time, full chip power benefits of negative capacitance FET (NCFET) device technology for commercial-grade GDSII-level designs. Owing to sub-60mV/decade characteristics, NCFETs provide significantly higher drive-current than standard FETs at a given voltage, enabling significant iso-performance power savings by lowering VDD. We use SPICE models of NCFETs corresponding to 14nm node, which incorporate experimentally calibrated models of ferroelectric. We then characterize NCFET-based standard-cell libraries followed by full-chip NCFET-based GDSII-level design implementations of different benchmarks. Our results show that even with increased device capacitance, we can achieve about 4× (up to 74.7%) full-chip power reduction with low-VDD NCFETs over nominal VDD baseline FETs at iso-performance. The power savings are consistent across multiple benchmarks and are higher for low power designs.

We enhance the capability of industry standard compact model BSIM6 to model the parasitic current$ I_{{\text {edge}}}$at the shallow trench isolation edge. Accurate, efficient, and scalable model for$ I_{{\text {edge}}}$is developed by finding the key differences between$ I_{{\text {edge}}}$and main device drain current ($ I_{{\text {main}}}$). It is found that$ I_{{\text {edge}}}$has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to$ I_{{\text {main}}}$. These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage.