A model of high-performance computers is derived from instruction timing formulas, with compensation for pipeline and cache memory effects. The model is used to predict the performance of the IBM 370/168 and the Amdahl 470 V/6 on specific programs,/and the results are verified by comparison with actual performance. Data collected about program behavior is combined with the performance analysis to highlight some of the problems with high-performance implementations of such architectures.

We have designed and built a computer terminal that provides low cost, high quality graphics and programmable text processing by taking advantage of the latest memory and microprocessor technology. A microprocessor control element allows most of the control functions to be programmed so that all of the control electronics require less than 100 integrated circuits. The graphic image is generated by a microprocessor which accepts vector commands intended for a Tektronix storage tube display terminal. The microprocessor maps those vector commands into a random access memory, and the resulting bit map of the graphic image is displayed on a standard TV monitor. Reasonable resolution in the graphic image requires a large number of bits in the bit map, but with the use of 4K memory chips, less than 100 integrated circuits are required for the bit map memory in our design. At 1975 small-quantity prices, the parts cost for the terminal is approximately $2000.

An algorithm that finds the k nearest neighbors of a point, from a sample of size N in a d-dimensional space, with an expected number of distance calculations is described, its properties examined, and the validity of the estimate verified with simulated data.