This paper presents a fully integrated continuous-scalable conversion-ratio (CSCR) switched-capacitor voltage regulator (SCVR), capable of supporting a wide range of voltage conversion ratios and high load current for SOCs used in computing and other applications. This design can achieve both step-down and step-up voltage conversion and has phase-merged turbo modes to deliver higher output current. It can autonomously and dynamically transition between step-down and step-up modes based on conversion ratio and between regular and turbo modes depending on load current. This SCVR is designed using Intel’s 3nm FinFET technology and is capable of an output voltage range of 0.5V-1.2V from an input of 1.1V. Furthermore, the input voltage can be in the range 1.1-1.3V for the same output voltage range. It can deliver up to 8A of load current at a 1GHz flying capacitor switching frequency and exhibits a peak efficiency of 88%. This design minimizes the added die area for the converter by implementing the flying capacitors over the load domain and achieves a maximum active area power density of 14W/mm$^{2}$. The converter uses a fast asynchronous voltage droop detector, in combination with auto-transition to turbo modes, to achieve excellent transient response-an output voltage droop of 37.5mV was measured for a fast (100ps) load current step from 0.1A to 6A. It also features configurable maximum switching frequency reduction and clock interleaving to achieve an output voltage ripple of 20mV.

There has been recent interest in exploring the acceleration of nonvectorizable workloads with spatially programmed architectures that are designed to efficiently exploit pipeline parallelism. Such an architecture faces two main problems: how to efficiently control each processing element (PE) in the system, and how to facilitate inter-PE communication without the overheads of traditional shared-memory coherent memory. In this article, we explore solving these problems using triggered instructions and latency-insensitive channels. Triggered instructions completely eliminate the program counter (PC) and allow programs to transition concisely between states without explicit branch instructions. Latency-insensitive channels allow efficient communication of inter-PE control information while simultaneously enabling flexible code placement and improving tolerance for variable events such as cache accesses. Together, these approaches provide a unified mechanism to avoid overserialized execution, essentially achieving the effect of techniques such as dynamic instruction reordering and multithreading. Our analysis shows that a spatial accelerator using triggered instructions and latency-insensitive channels can achieve 8 × greater area-normalized performance than a traditional general-purpose processor. Further analysis shows that triggered control reduces the number of static and dynamic instructions in the critical paths by 62% and 64%, respectively, over a PC-style baseline, increasing the performance of the spatial programming approach by 2.0 ×.

In this paper, we present triggered instructions, a novel control paradigm for arrays of processing elements (PEs) aimed at exploiting spatial parallelism. Triggered instructions completely eliminate the program counter and allow programs to transition concisely between states without explicit branch instructions. They also allow efficient reactivity to inter-PE communication traffic. The approach provides a unified mechanism to avoid over-serialized execution, essentially achieving the effect of techniques such as dynamic instruction reordering and multithreading, which each require distinct hardware mechanisms in a traditional sequential architecture.

A 1.75 MByte L2 cache has been designed and fabricated as part of the Alpha 21364 microprocessor[1] (Figure 1), in a .18m bulk CMOS process. The cache was designed to run at 1.2 GHz, and pass-1 samples confirm this. While Alpha CPUs are known primarily for high speed, the combination of package constraints and a tight schedule forced careful attention to the integrated whole of power expenditure and the interaction of CAD with design. The cache consumes only 7% of total die power.