Significant progress has been made in the past twenty years on the implementation of software-defined radios (SDRs) based on general purpose processors (GPPs). In contrast, there has been limited work on the analysis of the computational requirements of such SDRs. Quantifying the signal processing complexity in SDR is critical to ensuring that the system has sufficient computational resources to support reliable digital communications. Our contribution is to analyze and measure the computational cost of a Gaussian minimum shift keying (GMSK) transceiver based on GNU Radio, a widely used GPP-based SDR. Further, we introduce GNU Radio's working mechanism. To the best of our knowledge, our work is the first to provide detailed computational analysis of digital communications based on GNU Radio.

The combination of cloud computing, ad hoc networking and proliferation of wireless devices and sensors will be the most significant disruptive technology to transform the way next generation services are supplied and consumed in the communications industry since the introduction of Internet. In this next generation service marketplace, service brokering is emerging as a promising low-risk business model for offering new and value-added services through cross provider service delivery and partnership. The paper presents a service brokering architecture possessing the capabilities necessary to support a service delivery infrastructure for integration, delivery and management of composite services in a multi-provider heterogeneous networks environment.

This paper describes our effort to build extensible routers using a combination of general-purpose and network processors. We emphasize five overriding challenges that dictate our design decisions: (1) optimal resource allocation; (2) efficient but flexible scheduling of the CPU; (3) maintaining overall router robustness; (4) maximizing router performance; and (5) providing sufficient extensibility to enable the injection of new functionality into the router. We adopt a hierarchical architecture, in which packet flows traverse a range of processing/forwarding paths, thereby partitioning hardware and software in concert. This paper both presents the architecture, and describes our experiences implementing the architecture and addressing the five design challenges in a prototype built from Intel IXP 1200 and a Pentium. Copyright © 2005 John Wiley & Sons, Ltd.

Recent efforts to add new services to the Internet have increased interest in software-based routers that are easy to extend and evolve. This paper describes our experiences using emerging network processors---in particular, the Intel IXP1200---to implement a router. We show it is possible to combine an IXP1200 development board and a PC to build an inexpensive router that forwards minimum-sized packets at a rate of 3.47Mpps. This is nearly an order of magnitude faster than existing pure PC-based routers, and sufficient to support 1.77Gbps of aggregate link bandwidth. At lesser aggregate line speeds, our design also allows the excess resources available on the IXP1200 to be used robustly for extra packet processing. For example, with 8 × 100Mbps links, 240 register operations and 96 bytes of state storage are available for each 64-byte packet. Using a hierarchical architecture we can guarantee line-speed forwarding rates for simple packets with the IXP1200, and still have extra capacity to process exceptional packets with the Pentium. Up to 310Kpps of the traffic can be routed through the Pentium to receive 1510 cycles of extra per-packet processing.