This work extends previous work on run-time tracing of the design activity in order to handle dependencies between design data in a uniform way, including requirements and deliverables. Each requirement is stored in a card; several cards are organized into linear hierarchical stacks. The system offers: requirement tracing, impact analysis, support for requirement analysis, automatic retracing. The contributions are: (1) the run-time property, which assures a detailed representation of dependencies, (2) the linear organization of the stacks of cards, and (3) the uniformity with which all design data, from requirements to deliverables, are treated. A prototype has been used in a real design.

An automatic management system for CAD based on the idea that CAD tools can leave a trace of their execution is proposed. The trace, represented as a bipartite directed and acyclic graph in which the nodes represent either design data or tool invocations, is both a record of the design activity and a graph representing the dependencies among the design objects. The architecture of the proposed system is distributed. A server manages the trace, while a number of clients can concurrently interact with the trace through the server. The system is nonintrusive, because it does not affect the way designers interact with the tools. The design manager has been implemented in a system called VOV, which has been tested.>

VOV is an automatic manager for VLSI design. It is based on the idea that CAD tools can leave a “trace” of their execution. The trace is represented as a bipartite directed and acyclic graph, in which the nodes represent either design data or CAD transactions. By managing and analyzing the traces, VOV offers a wide variety of services related to design management, such as coordination of team design, automatic execution of CAD transactions, capture of design history and data dependencies. All of these services are provided in a non-intrusive fashion. VOV has the notion of measurement on the design data, an ingredient which is necessary to provide even more services: tracking of design specifications, validation of design data, design estimation.

A modification of the classical Simulated Annealing algorithm for the macro-cell placement problem is proposed for implementation on multiprocessor systems. The algorithm has been implemented on the Sequent Balance 8000, a multiprocessor system with a shared-memory architecture. Experimental results show that the new algorithm obtains results comparable in quality to those of the single processor version; processor utilization is greater than 80 percent using up to eight processors.