By we continuously observe the entire earth with artificial satellites, it will be possible to accurately know the time-series changes in observation data for each region. In addition, it is possible to obtain knowledge that cannot be obtained by observation from the ground, such as local weather changes. These data are used to understand the global climate change in each region. It is very important that researchers get earth observation data as soon as possible. This is because we can greatly contribute to the progress of understanding on global environmental changes. We introduce two examples of satellite data processing using the JAXA supercomputer system (JAXA Supercomputer System Generation 2, hereinafter JSS2) and explain that JSS2 is an effective system for satellite data processing. In addition, we explain the prospect of satellite data processing using the next JAXA supercomputer (JAXA Supercomputer System Generation 3, hereinafter JSS3).

Recently, increasing power usage of HPC systems is a critical issue. Therefore, effective power saving method for eliminating electricity waste are very important to develop.

The use of PC cluster systems composed of many PCs is largely spread in these days. If there are many waiting jobs even when there is free resource, it is a waste of resource. So the algorithm to execute jobs as many as possible has been researched for decades. However this optimization problem is difficult to solve. So we propose algorithms based on a strip packing problem to arrange jobs. We performed numerical experiments and we show these results.

Fast Aerodynamics Routines (FaSTAR) is one of the most recent fluid dynamics software package. The problem of FaSTAR is hard to be executed in parallel machines because of its irregular and unpredictable data structure. Exploiting reconfigurable hardware with their advantages to make up for the inadequacy of the existing high performance computers had gradually become the solutions. However, a single FPGA is not enough for the FaSTAR package because the whole module is very large. Instead of using many FPGAs, partially reconfigurable hardware available in recent FPGAs is explored for this application. Advection term computation module in FaSTAR is chosen as a target subroutine. We proposed a reconfigurable flux calculation scheme using partial reconfiguration technique to save hardware resources to fit in a single FPGA. We developed flux computational module and five flux calculation schemes are implemented as reconfigurable modules. This implementation has advantages of up to 62.75% resource saving and enhancing the configuration speed by 6.28 times. Performance evaluation also shows that 2.65 times acceleration is achieved compared to Intel Core 2 Duo at 2.4 GHz.

FaSTAR developed by JAXA is a leading edge CFD (Computational Fluid Dynamics) program package which supports various solvers based on unstructured grids. The computation based on unstructured grid causes a lot of pipeline stalls by RAW (Read After Write) hazard when reconfigurable accelerators are implemented in FPGAs. In order to cope with this problem, the OoO (Out-of-Order) mechanism generator is proposed. By setting parameters depending on the target computation, the OoO mechanism with appropriate structure of the execution unit and waiting buffer is generated. The OoO mechanisms are applied to five subroutines in FaSTAR, and it achieved 2.6 times performance as the case of in-order execution, and 2.9 times as the software executed by Intel Core2Duo processor with reasonable amount of overhead.

CFD is taken notice as a cost effective design tool for aircraft components. UPACS is a convenient CFD platform, since it supports a large degree of versatility using various kinds of solvers. However, its major drawback is a long simulation time. We have developed a UPACS accelerator named FLOPS-2D with multiple FPGA boards, and implemented some core functions. Here, by using flexibility of FPGAs, the selectable functions are proposed. All possible flux limiter functions in MUSCLs are implemented independently, and only required functions are selected and implemented with other modules to form the optimal structure. All implemented functions achieved at least 24 times higher performance than that with the Core 2 Duo, and configurable solvers using a desired flux limiter function and the number of arithmetic pipelines are developed.

Computational Fluid Dynamics (CFD) is an important tool for aeronautical engineers. Instead of expensive super-computers or clusters, using custom pipelines built on FPGAs is expected to be a cost effective solution to accelerate CFD. The problem is that to keep the pipeline busy is difficult because of the memory bandwidth. To deal with this problem, an effective memory access method using Block-RAMs is implemented based on a careful survey about memory access pattern. This work is targetting on two major subroutines in UPACS, a CFD software package. As a result, the amount of data transfer is reduced about 40%. This shows 46–170fold speed-up is expected by several Virtex-4 FPGAs compared to Itanium2 processor.

SRFS on Ether adds an ethernet interface to the Shared Rapid File System (SRFS) that is currently used as a distributed file system between nodes by the HPC-system. It can be used like NFS and has solved the problem of data coherency in the high-speed transmission of data in a broadband environment, which NFS has not. Moreover, adjustment of the TCP/IP parameters in the OS to improve speed is unnecessary, and special hardware is not needed, unlike with the SAN construction by iFCP and others. For additional speed, it stripes data streams automatically (default MAX 8 streams), switches protocols between TCP and UDP based on IOsize.In this bandwidth challenge, we demonstrate security using a host-to-host IPSec connection between Tampa and Tokyo. To show performance, we used a hardware IPSec accelerator and tuned TCP/IP with SRFS on Ether's.