Cascading gain stages in CMOS Operational Transconductance Amplifiers (OTAs) has become a necessity in applications with high gain requirements, where the contribution of each stage to the overall gain is well-known and carefully designed. Many of these applications also impose requirements on speed, including a minimum Slew-Rate (SR) to ensure signal fidelity, however the impact of individual gain stages on the overallSRin multi-stage OTAs has been difficult to characterize–let alone carefully design. The difficulty arises due to the complexity of the compensation networks involved in these OTAs. This paper presents a systematic design approach for achieving a targetSRin multi-stage CMOS OTAs, enabled through the utility of a novel analytical model for estimating the lower-bound Slew-Rate in multi-stage OTAs. The model evaluates individual currents and equivalent capacitances at the output node of each stage, providing insights on the dominant node slowing down the overallSR. For generality, the model establishes theSRanalysis based on N-stage designs, and considers widely employed compensation networks. Example designs, with post-layout simulations and measurements of a 3- and a 4-stage CMOS OTA, and with post-layout simulations of a 5-stage CMOS OTA, are presented for validating the model’s utility. The results show strong agreement between theoretical, simulated, and measuredSRvalues, confirming the model’s reliability in estimating the lower-boundSR, and its utility in a systematic design-for-SRapproach in multi-stage CMOS OTAs.

Analog test buses facilitate the testing of analog components in integrated circuits through dedicated test ports and switches. IEEE 1149.4 is an analog test bus standard that can be calibrated with simple gain correction but cannot calibrate for other sources of error present at higher frequencies, leading to inaccurate measurements. This paper presents a novel analog test bus structure with greater calibration capabilities inspired by the vector network analyzer (VNA) calibration approach that uses multiple known calibration references. These references were integrated within the test bus constructed of voltage and current buffers. IEEE 1149.4 and the proposed test bus were first compared via simulation and then through a discrete component PCB implementation, both aimed at measuring a transimpedance amplifier (TIA). The simulation showed that the proposed test bus exactly measured the amplifier with little error while 1149.4 deviated at higher frequencies. These results were echoed in the physical experiment, with the proposed 4-port deviating slightly from the ideal due to the mismatch inherent in the PCB experiment.

The gain and bandwidth of a shunt-feedback Transimpedance Amplifier (TIA) is limited by a so called transimpedance (TI) limit. This limit dictates the maximum possible value of the feedback resistance (RF) for a targeted bandwidth. Additionally, the input referred noise of such TIAs is inversely proportional to theRF, which presents a challenge in simultaneous optimization of bandwidth, noise and transimpedance gain. In this paper, the TI limit is revisited, and a multi-stage RC compensation technique is presented for the design of the open-loop amplifier for a closed-loop shunt-feedback-based TI stage. This paper shows that with the appropriate pole-zero positioning, the DC transimpedance gain can be decoupled from the closed-loop TI bandwidth. This is achieved by placing a zero in the open loop transfer function to reduce the impact of the closed loop dominant pole created by the input capacitance and the RF. As a result, without the need for area consuming inductors, a TI stage is realized which has a transimpedance limit that is larger than the conventionally assumed limit. Additionally, the proposed RC compensation network provides more control over the pole-zero positioning which results in smooth overall frequency response after equalization. This is verified by experimental results which show that the proposed technique achieves a much greater transimpedance gain as compared to that of the conventional limit while reducing the noise and without any significant deterioration of bandwidth. The design has been implemented in a 90 nm BiCMOS process from Global Foundries (GF-9HP). A detailed comparison of the proposed approach is presented with other TIA designs. As per the author’s best knowledge, the proposed design outperforms the state-of-the-art TIA designs in terms of the noise-transimpedance-bandwidth trade-off.

This paper presents an inductorless fully differential and linear design of continuous time linear equalization (CTLE) to simultaneously optimize the bandwidth and noise of transimpedance amplifiers. The proposed CTLE is implemented with RC components in a negative feedback configuration. The proposed design is compared with the conventional CTLE approach that uses an inductor-based implementation. The comparison suggests that the proposed CTLE not only achieves the same equalized bandwidth but also results in less group delay variations as compared to its inductor-based counterpart. Additionally, a TIA is designed using the proposed CTLE approach in GF-BiCMOS 90 nm$(\mathbf{f}_{\mathrm{t}}=\boldsymbol{310}$GHz) process and its performance is verified by post-layout simulations which include the loading effects of photodiode and$50-\Omega$output loads. As per the authors' best knowledge, the proposed TIA design is the first of its kind in the sense that without the use of inductors in any stage, it can support up to 80 Gb/s NRZ data stream with a transimpedance gain of 72$\mathbf{dB}-\Omega$and an input-referred noise density of about 1.25 pA/sqrt(Hz).

This work introduces a multi-stage CMOS OTA design technique that allows cascading identical gain stages (for arbitrarily scalable high DC gain) while driving an ultra-wide range of capacitive loads ($\text{C}_{\text {L}}\text{s}$). At the heart of the proposed design is a new frequency compensation technique (FCT) that relies on low-frequency left-half-plane zeros to allow the proposed OTA to operate for a desired closed-loop behavior. In this work, classical gain-stages (i.e., differential pair and common source transistors) are used to design fully-differential 2-, 3-, 4- and 5-stage CMOS OTAs. The proposed 2-to-4-stage designs have been fabricated in TSMC 65 nm CMOS process and the measurement results show that the 2-stage OTA is achieving a DC gain of 50 dB with a$\text{C}_{\text {L}}$-drivability ratio (i.e.,$\text{C}_{\text {L,max}}/\text{C}_{\text {L,min}}$) of$10,000\times $, the 3-stage OTA is achieving a DC gain of 70 dB with a$\text{C}_{\text {L}}$-drivability of$1,000,000\times $, and the 4-stage OTA is achieving a DC gain of 90 dB with a$\text{C}_{\text {L}}$-drivability of$1,000,000\times $. This is a 10-to-1000-time improvement in the state-of-the-art, as the highest$\text{C}_{\text {L}}$-drivability reported to date is$1000\times $. Accordingly, the proposed OTAs can cover a wider range of applications than any other reported works.

This work introduces a new design technique for extending the load driving capability of conventional Miller-RC CMOS OTAs, up to nF-range capacitive loads (CL), with near-optimum small- and large-signal time responses. The proposed technique involves modifying the R-C compensation network such that the unity-gain frequency, æt, of the OTA is highly increased. This additional increase in ωtcan then be traded-off for higher loads by transferring the dependency of the dominant pole to CL. To implement and verify the proposed technique, the classical differential-ended two-stage OTA was used as a design example in order to drive a load of 1000 pF. Interestingly, with the modified compensation network, an area efficient design was achieved, demonstrating excellent performance.

In this work, a new scalable CMOS OTA design that systematically enables cascading many identical OTA stages is proposed. This scalable design of the many-stage OTA ensures stability, when configurated in closed loop, by means of a new scalable frequency compensation technique. The presented design realizes a CMOS OTA with scalable-gain that increases in 25 dB increments per stage, achieving a total gain from 50 dB to 150 dB for a 2-stage to a 6-stage OTA, respectively. Stability of the many-stage OTA is ensured by re-positioning the poles and zeros of all gain stages in a systematic scalable pattern whenever a new gain-stage is added. The presented design was based on a TSMC 65 nm CMOS process.

Stability analysis of analog circuits that incorporate single-loop feedback is often associated with determining the loop transmission Aβ and subjecting it to the Nyquist stability criterion. Various techniques have been developed to extract Aβ from a circuit. However, proper application of the Nyquist stability criterion requires information about A and β separately, before establishing their product. This paper will present a method to identify the feedback parameters A and β of a circuit without breaking the loop unlike any other method seen previously. A second-order filter example will be provided to justify the proposed method.

The presence of RLC line parasitics in a flexible hybrid electronic assembly can lead to signal integrity issues, and their progression over time can lead to catastrophic failures. A technique for extracting the RLC line parasitics from a flexible hybrid electronics assembly is presented. The proposed extraction method exploits the on-chip ESD protection circuits of an IC chip to extract the parasitics of the printed conductors bonded to the chip. This is performed through a single test access port, i.e., two test points. While the parasitics LC are extractable through one-port reflection-based techniques such as time domain reflectometry; the parasitic R requires a two-port measurement such as Kelvin test, which is extremely difficult to perform for printed conductors bonded to small surface-mount IC package devices. The accuracy of the extracted RLC parameters with the proposed method are verified with a prototype developed on a rigid FR4 substrate. Subsequently, the proposed technique is utilized to track the variation of the RLC parasitics for prototypes developed on Kapton Polyimide substrate subjected to different forms of bending.

The presence of Pole-Zero (P-Z) pairs in the open-loop frequency response of CMOS OTAs has always been considered detrimental to the closed-loop operation of OTAs. In this work, a new proposed theory is presented showing how to reduce the impact of such P-Z pairs on the settling time of CMOS OTAs - using low-frequency zeros and cascaded-gain stages - consequently revealing un-tapped opportunities for many-stage CMOS OTA design. The proposed theory will be validated and verified through a design example that also demonstrates how the generalized theory unveils opportunities for many-stage OTA design. The presented example is a 2- to 8-stage CMOS OTA based on the TSMC 65 nm CMOS process, verified through simulations (schematic and post-layout) as well as some measurement results.

Sigma–delta ($\Sigma \Delta$) digital-to-analog converters (DACs) are commonly used to realize programmable dc voltage generators in built-in self-test (BIST) schemes, largely on account of their high linearity. Unfortunately, such$\Sigma \Delta $-DACs require large amounts of digital memory and a reconstruction filter with a large silicon area footprint. In this article, a segmented DAC architecture is proposed. The proposed architecture is realized using two sub-DACs, where both are$\Sigma \Delta $-based. This DAC provides two advantages: filter footprint size reduction and memory savings, thereby allowing for a simpler BIST solution. The benefits of using the segmented$\Sigma \Delta $-DAC are shown using two experimental prototypes. The first is an IC prototype design using the TSMC 65-nm CMOS technology. It will be shown that the IC achieves 12 bits of resolution from 1020 memory elements, whereas an unsegmented$\Sigma \Delta $-DAC uses 4095 elements to obtain the same resolution. This is about a 75% savings in memory elements. The segmented prototype occupies 0.5 mm2of silicon area, whereas the unsegmented design occupies 0.77 mm2for the same resolution. A 35% silicon area savings compared with its unsegmented counterpart. A second prototype implements the segmented$\Sigma \Delta $-DAC architecture using discrete components. The discrete prototype achieves 16 bits of resolution from 1020 memory elements, whereas the unsegmented counterpart uses 65 535 bits for the same resolution. This is a 98% saving in memory elements.

An in-situ technique is presented for measuring the individual contact resistance between the pins of an IC package and a flexible substrate used in hybrid electronic systems. As the substrate flexes, the forces that adhere the IC to the substrate change and cause increase to the series contact resistance; sometimes catastrophically. Tracking this resistance is seen to be fundamental to the success of electronic systems mounted on a flexible substrate subjected to various levels of bending throughout its life cycle. The measurement technique exploits the electrostatic discharge protection circuitry in an IC chip to create a circuit loop involving the contact resistance and the series incremental resistance of the ESD circuit via two IC pins, one being the GND or VDD pin. While the series contact resistance between the pins of the IC package and the board can be measured with a four-point Kelvin measurement, it is extremely difficult to perform with small surface-mount IC package devices. The experimental results pertaining to Kapton polyimide substrate subjected to a controlled bending process will be described. The method proposed here will determine the contact resistance with a relative accuracy error of less than 1%.

In this paper, a novel programmable time-difference amplifier (TDA) with femtosecond resolution is presented. The proposed TDA design cascades three time latches and digital gates to amplify the input time difference with selectable gains. The time gain is simply determined by changing digital switches performing time addition. Based on digital gates, the proposed circuit achieves performance comparable to the state-of-the-art TDAs, without the limitations of analog components imposed by scaled CMOS processes. The proposed TDA is simulated in a 1V 65 nm TSMC CMOS process to validate the accuracy of the proposed architecture. The linearity of the proposed TDA is verified from 150 fs to 200 ps with a gain error of less than ±4%, while consuming 519 μW with a 450 MHz clock frequency.

This paper presents a coherent subsampling test system arrangement that can be configured to measure the intrinsic noise and jitter transfer characteristic response of a time-based channel. Such as a phase-locked loop using a sampling rate that is established based on the incoming signal bandwidth rather than the highest frequency contained in the measured signal. These test systems are applicable to a wide range of applications from RF to optical communication systems and can be constructed using off-the-shelf components. Experiments conducted on a Teradyne Flex tester are used to validate the proposed subsampling principles.

This paper derives the equations leading to the analytic expression of the frequency spectrum at the output of multi-bit delta-sigma modulators afflicted by component mismatch in the digital-to-analog converter used in the feedback path. The effect of the mismatch is modeled as an error signal added to an ideal digital-to-analog converter. The frequency content of this error signal is derived from the probability density functions of the input signal and the shaped quantization noise. The analysis is applied to band-limited Gaussian input signals. Several simulation results are reported, showing a 0.3 dB accuracy of the analytic expressions whenever the number of quantization bits is higher than two.

While printable electronics (PE) has the potential to provide a low cost means to manufacture electronic solutions, it suffers serious levels of component variations. While many of the problems facing PE are early technological development yield-related problems, some are more fundamental to its manufacturing nature. In this work, methods to construct PE circuits that compensate for these variations will be described. These methods include a combination of printing, severing, and ink deposition techniques that are performed both during and after manufacturing. Data obtained from working prototypes made using the PE technology at the National Research Council (NRC) of Canada will be described.

In this article, a method of designing high-order DLLs is presented and verified through both simulations and physical experiments. The general approach is based on selecting the transfer function of the closed-loop DLL and deriving the loop filter behavior based on the gain of the phase-detector and voltage-controlled delay line. The proposed approach does not rely on the principle of design based on achieving a desired phase margin specifications but rather is based on selecting a closed-loop DLL behavior based on a desired Gaussian transfer function. Experimental results are provided to support the claims.

Analog/Mixed-Signal test is usually thought of as a quality control step in the manufacture of electronic devices - largely to separate good devices from bad. In this paper, the case is made that analog/mixed-signal semiconductor test technology has been at the forefront of many of today's analog SOC design approaches. This is most likely quite opposite to what most engineers think about test. The reason is quite simple - analog test engineers are concerned with a multitude of design issues that span across many different engineering domains such as mechanical, electrical, electronic, firmware and software. Moreover, they have always been pressed to achieve accurate measurements in near minimum time. As a result, analog test engineers have always had their eye on the big picture and created test solutions decades ago that would rival any analog system platform today. This paper will take a look to the past and see how test technology has impacted present-day system approaches such as those used in data communications, general purpose analog signal processing, etc.

An instrument for on-chip measurement of transceiver transmission capability is described that is fully realizable in CMOS technology and embeddable within an SoC. The instrument can be used to inject and extract the timing and voltage information associated with signals in high-speed transceiver circuits that are commonly found in data communication applications. At the core of this work is the use of ΣΔ amplitude- and phase-encoding techniques to generate both the voltage and timing (phase) references, or strobes used for high-speed sampling. The same technique is also used for generating the test stimulant for the device-under-test.

This paper presents a complete methodology to model, design, and implement wide tuning-range phase-locked loops (PLLs) using a top-down approach. Mathematical equations that illustrate the contribution of the different sources of noise in the PLL are presented. Behavioral models that encompass the nonidealities of the PLL components are described using Verilog-A language. The PLL components are designed, and the noise performance of each component is evaluated using transistor-level simulations. The extracted jitter from the individual blocks is used to find the overall system noise. The proposed methodology considers the variations in the loop dynamics due to changes in the voltage-controlled oscillator gain and noise, frequency divider ratio, and charge pump current. While optimizing the PLL for maximum tuning range, the methodology also considers the tradeoff between the noise, speed, and reference spurs attenuation. The design and implementation of an integer-N frequency synthesizer PLL that covers a continuous frequency range from 156.25 MHz to 10 GHz using a 65-nm CMOS technology is demonstrated in this paper. Measurement results to verify the accuracy of the models and to validate the predictions made by the simulations are provided.

An operational-transconductance-amplifier (OTA) design for low-voltage low-power applications is proposed. The proposed OTA incorporates bulk-driven MOS transistors in the pseudo differential pair of the input stage to concurrently enable low voltage operation and rail-to-rail input range. Using a common-mode feedforward (CMFF) circuit in the first stage to bias the following stages of the OTA obviates the need for extra biasing circuitry and improves the performance of the OTA. To further enhance the bandwidth and allow the use of smaller compensation capacitors, a compensation network based on a damping factor control circuit is exploited. To verify the theoretical findings, the OTA was fabricated in a 65 nm CMOS technology. Measurements show that the OTA provides a low-frequency gain of 46 dB at VDD= 0.5 V, and a gain of 43 dB at VDD= 0.35 V. The power dissipation is 182 μW at VDD= 0.5 V, and 17 μW at VDD= 0.35 V.

As circuits become increasingly complex and testing time continues to increase, it is becoming more and more important to use built-in self-test techniques to ensure that the circuit is working according to its data sheet specifications. This paper presents an embedded test instrument in an IBM 130 nm CMOS technology, which allows for quick and easy probabilistic test evaluation of the bit-error ratio of a device-under-test.

A voltage-controlled delay unit (VCDU) for low-voltage time-mode signal processing is presented in this paper. The proposed VCDU uses a signal conditioning circuit to achieve wider-range and higher linearity than state-of-the-art VCDUs. Circuit-level simulations in 0.18μm CMOS process show a linearity error of less than ± 0.2% for a 0.15 V to 1 V input range. The proposed VCDU consumes 315 μW from a 1.8 V supply at its maximum sampling frequency of 500 MHz. The proposed VCDU is validated in a first-order time-mode ΔΣ modulator application. Circuit-level simulation results of the ΔΣ modulator show a peak SNDR of 58 dB when clocked at 140 MHz with a 400 kHz bandwidth.

This paper proposes the use of an instrumentation layer in the die stack of a 3D-stacked IC for making precision on-chip measurements for silicon debug, device ramp-up and calibration purposes. As the instrumentation die communicates with the IC stack via the 1149.4 test bus, it can be removed from the stack to reduce the overall cost of the IC when in full production mode. Design effort on a full suite of analog instruments can be performed once and shared between different IC implementations, thereby reducing development costs. The initial focus of this work is on the development of a set of instruments that will be used to characterize the through-silicon via(s) (TSVs) of a 3D-CMOS process. Circuit details related to the design of a 3D-SIC using the Tezzaron 2-Tier 130 nm CMOS process are outlined.

Time-Mode Signal Processing (TMSP) techniques are attempting to develop analog signal processing algorithms using primitive digital building blocks such as inverters and NAND/NOR gates. By doing so, the design of such analog circuits can be captured and automated by standard digital design tools and methodologies. In this paper, a method is proposed for designing high-order elliptic filters based on the operational simulation of LC ladder networks using a set of all-digital timemode building blocks (some new, some known). The design of a fifth-order elliptic filter having 1 dB passband ripple and 60 dB of stopband attenuation will be used to demonstrate the feasibility of the proposed design method.

The productivity gap between analog and digital circuit design has been steadily increasingly over the past four decades of semiconductor development, largely driven by advances in digital CAD. Using a simple design productivity metric, like the number of transistor utilized per man-months for any given design, the analog team can incorporate anywhere between 10 - 100 transistors per man-months whereas the digital design team can utilize 100's of thousands or more per man-months. It is the objective of this paper to describe how time-mode signal processing can be used to reduce the analog-digital productivity gap and, in addition, consider how time-mode signal processing can assist with manufacturing considerations like analog/mixed-signal production test.

This paper presents an approach to fully characterize a transistor in any CMOS technology using a set of dimension-independent parameters. The proposed approach creates a layer of abstraction that circumvents the SPICE transistor model complexity and replaces it with a set of normalized parameters. The proposed approach combined with the designer's knowledge of the circuit operation facilitates solving for near optimal, if not optimal, circuit behavior. The required small and large-signal behavior is achieved, while the dc biasing at each node in the circuit is defined at the same time. A simple design tool, called ACDNP, based on the proposed concept was developed. The results predicted by ACDNP and the Spectre circuit simulator are in excellent agreement.

It is our privilege to welcome you to the 44th IEEE International Test Conference (ITC) sponsored by the IEEE Computer Society and the Philadelphia Section. We are pleased to once again return to the Disneyland Resort Hotel in Anaheim, California - a great venue for ITC, the world's premier conference in test.

At the 1999 ITC, Pat Gelsinger from Intel delivered an important keynote address where he outlined the need for a low-pin count tester with lower performance pin electronics to meet the stringent test cost requirements of a billion transistor machine. At the 2009 ITC, engineers from AMD came forward with an I/O test solution that is believed to meet the Intel challenge using a cash-resident self-testing strategy combined with an external low-pin count tester. How can we drive major challenges to post-silicon validation and in huge variance era? Technology scaling enables us to trade off amplitude resolution for time resolution. Accordingly, both internal and external tests, some of which use low-pin count testers, are also shifting from voltage centric tests to timing centric tests. How can time resolution be used to push the timing centric tests beyond current limitations? How can spatial resolution be realized to enhance yields in terms of both die-to-die variations and within-die variations? What is necessary to provide robust on-chip solutions subject to huge variations, which may be combined with an external low-pin count tester?

In this paper we present a design and implementation of an instrument that can be used to inject and extract the timing information associated with signals in high-speed transceiver circuits used for data communications. Using statistical methods, the probability distributions associated with these signals can be extracted using some digital logic and various low-pass filter circuits. At the core of this work is the use of ΣΔ encoding techniques to create both the voltage (amplitude) and timing (phase) references, or strobes used in high-speed sampling. Experimental results reveal the sampling time strobe can be programmed over a phase range of 45 degrees with a phase step of 1 degree at a fixed voltage reference. The probabilistic approach is shown to be extendable to input-output based testing, in general.

This paper presents a CMOS track and hold amplifier (THA) designed and fabricated in a 130 nm CMOS technology. It is intended for analog-to-digital converters (ADCs) used in radio receivers that sample in the Giga-Hertz region. At these data rates, it is extremely difficult for data converters to reach the desired performance levels using a single data path. Rather, ADCs operating in parallel at lower clock rates are becoming the norm. Such architectures require high-performance THAs capable of capturing the signal information at the desired sampling speed. Experimentally, this work will demonstrate a 2.5 GS/s THA capable of offering an SNR of almost 46 dB, SNDR of 42.4 dB and an ENOB of almost 7 bits.

This article presents methods and circuits for synthesizing test signals in the time/frequency domain. An arbitrary signal is first encoded using sigma–delta modulation in the digital amplitude-domain and converted to the time or frequency domain through a digital-to-time converter (DTC) or digital-to-frequency converter (DFC) operation realized in software. In hardware, the resulting bit-stream is inputted cyclically to a high-order phase-locked loop (PLL) behaving as a time-mode reconstruction filter in the appropriate domain (time or frequency). A high-speed prototype implementation consisting of a 4th order PLL built in 0.13 μm complementary metal oxide semiconductor (CMOS) process with an off-chip loop filter has been fabricated and used to generate signals at 4 GHz. The digital nature and portability of the phase/ frequency test signal generation process makes the proposed scheme compatible with the IEEE 1149.1 test bus standard and easily amenable to any testing environment: production, characterization, design-for-test (DFT), or built-in self-test (BIST).

This paper presents the design of several low-pass IIR time-mode filters for use as reconstruction filters in digital-to-time conversion (DTC) applications. Previously, such reconstruction filters were implemented using phase-locked loops. The proposed filters are constructed from a simple digital-like structure involving voltage-controlled delay units. The resulting circuits require very small silicon area and consume very little power. A first-order filter design for wideband reconstruction applications was fabricated in a 0.13 µm CMOS process occupying a silicon area of 170 ¼m x 100 ¼m and consumes 670 mW. Another design, intended for narrowband sigma-delta phase signal generation applications, is proposed that utilizes similar building blocks, but uses a filter topology that is better suited for transfer functions with high-Q poles. High-order realizations can be constructed as the cascade of several first-order sections. Such an approach will be demonstrated in the design of a sigma-delta phase encoding signal generation scheme.

In this article, an accurate and low-cost clock delay generation system integrated in an automated test equipment (ATE) environment is presented. The input to this system is entirely digital and is driven by a single clock, which can be programmed from the ATE High Speed Digital (HSD) unit. Moreover, the digital input patterns can easily be generated in software off-line; hence, making this system ideal for automated test routines. The system is first discussed and characterized in Matlab under static and dynamic operating conditions. For the static behavior, the impact of the various design tradeoffs on the time resolution is investigated. With regards to the dynamic behavior, the linearity is assessed spectrally with a sinusoidal input and statistically using a Gaussian noise signal. A discrete prototype board is built to validate the correct operation of the system mounted on an ATE to function as a whole. With proper compensation and calibration, a delay resolution of 15 ps was achieved over an 8.4 ns range using a low-speed reference clock running at 16.67 MHz. It is shown through clock scaling that this resolution can improve in direct proportion to increases in the clock frequency.

A new technique and circuit topology is proposed to readout the output of a capacitive sensor for lab on chip (LOC) applications. Using time-mode signal processing and adopting modified digital blocks, a first-order delta-sigma interface is developed. It offers an incredibly compact and low-power solution where analog precision is achieved by making advantage of digital design. The design is capable of being tuned for different ranges of input capacitance as well as different resolutions where applicable. The proposed circuit is layout in 0.8-mum DALSA CMOS process. Post-layout simulation shows a capacitance change of 5 fF can be measured with error less than 2% in 500 mus. Also, the resolution of the circuit can be increased by 25 times to measure an input capacitance as small as 0.2 fF.

The design of a second-order low-pass IIR filter based on time-mode signal processing circuits is presented. The filter is implemented using a set of building blocks that perform basic mathematical operations in the time-domain including time addition, weighted delayed time addition and subtraction, and unit delay. A second-order low-pass Chebyshev filter was designed in a 0.18 mum CMOS process. Simulation results confirmed that the design can achieve low-pass filtering, providing a maximum SNR of 63.6 dB and SNDR of 44.1 dB.

This paper presents a method that optimizes the performance of CMOS amplifiers with respect to gain, bandwidth, noise, distortion and power. The method is performed directly in SPICE without the aid of mathematical models or external software routines. The method works in all SPICE programs from Cadence to the student version of PSPICE. The technique is based on tuning the voltage of specific nodes of the amplifier using a servo-loop biasing technique in conjunction with a replica amplifier circuit to span the entire performance space with a resolution of choice. Both single-stage and multi-stage amplifiers are considered in this work.

Time-to-voltage converters (TVCs) exploit a digital circuit to convert the time difference between the edges of two digital signals into a single digital pulse whose pulse width is equal to this time difference. This pulse is then used as the control signal that controls the charging duration of a current source-capacitor combination. In all previous TVC designs, the digital circuit consists of a chain of registers, which has a potential metastability hazard. This paper proposes a new architecture of the digital circuit which is independent of this hazard. The circuit was designed in a standard 0.18-μm CMOS process and verified on a Teradyne FLEX tester at a resolution of 39.0625 ps. Experimental results also reveal that the output of the digital circuit is independent of the metastability effect.

In this article, a low-cost, high-frequency signal generation procedure suitable for Noise Power Ratio (NPR) and Adjacent Channel Power Ratio (ACPR) test is presented. The proposed technique can be implemented with any ATE equipped with a memory block and digital source in conjunction with a high frequency and high attenuation analog filter; hence, a costly external source is not required. The technique consists of digitally encoding the noise signal having the specified power spectrum using pulse-density modulation and recovering the analog stimulus with an analog filter operating in the desired spectrum. The technique is validated by simulation and experimental results. In simulation, both NPR and ACPR stimulus were realized with a 100 dB specification. For NPR test stimulus generation, a notch depth of 60 dB with respect to the noise pedestal was experimentally achieved. The sensitivity of the proposed methodology to jitter is also investigated.

A new architecture and signal processing methodology is proposed to implement a first-order single-bit delta-sigma (ΔΣ) analog-to-digital converter (ADC). The proposed design converts an analog input voltage into a time-difference variable and performs the ΔΣ signal processing in the time-mode. This offers an incredibly compact and low-power ADC solution while thriving in a low-voltage CMOS environment. The proposed design was fabricated in a standard 0.18-μm CMOS process occupying a silicon area of 15-μm × 25-μm and consumes 475-μW of power. Experimental results reveal that the design can provide a 7-bit resolution at a sampling rate of 140-MHz and input bandwidth of 400-kHz.

An embedded diagnosis circuit for quantifying the degradation in digital signals rise/fall time is presented. The proposed measurement technique differs from previous approaches in many ways. Firstly, it avoids the use of undersampling which can become problematic at high speeds; instead, it relies on a real-time asynchronous sampling approach which eliminates the distortion jeopardy imposed by the front-end sampling network, sampling clock jitter, and delay line jitter for GHz range applications. Secondly, the information is processed in the time domain which makes use of the recent developments in time-domain amplification (Oulmane and Roberts, 2004). Thirdly, a dynamic current generation technique is used to achieve great reduction in static power dissipation and allows the front-end level-crossing detector to work at such high speeds. The circuit was implemented in a standard 0.18-mum CMOS process. Simulation results show the feasibility of the proposed approach. Preliminary experimental results are also presented. The proposed circuit can be equally used to perform on-chip analog slew rate measurement

A comparator design methodology is proposed that is digitally calibrated for process variability and digitally-synthesizable. The proposed comparator design was fabricated in a 0.18-mum CMOS process. Experimental results demonstrate that the comparator does compensate for process variation, with an 8-bit resolution while operating at a sampling rate of 25 MHz

A robust programmable analog Gaussian noise generator suitable for mixed-signal/digital ATEs is presented. Unlike conventional methods (LFSR based noise generators or resistor thermal noise amplification techniques), the user has full control of the characteristics of the Gaussian signal. Indeed, the frequency band, the mean, and variance of the distribution are fully programmable over the voltage range within the supply rails. The method consists of digitally encoding the specified Gaussian signal in a RAM, using pulse-density modulation, followed by filtering the bit stream using an analog low-pass filter. It is demonstrated that the quality of the generated noise signal is independent of the quality of the filter used; hence, making the noise source highly robust. The output of the noise generator accurately models a real Gaussian signal, even at high sigma values; thus, making it a very effective and predictable dithering signal. Two applications of the proposed Gaussian noise source are demonstrated: ADC histogram testing and high-resolution digitization

Noise, especially clock jitter effects, in a DSP-based mixed-signal test system severely limits its measurement accuracy. This is especially acute in high-frequency sampling systems. This paper illustrates an efficient method to improve measurement accuracy and precision by reducing the uncertainty of a DSP-based measurement without an increase in test time. A new digitizer architecture is introduced. The digitizer was fabricated in a 0.18-/spl mu/m CMOS process. Experimental results were obtained validating the proposed technique.

A compact timing and jitter test system that leverages custom integrated circuit measurement methods and localized test result processing is presented. It consists of five timing measurement units (TMU) and five timing generation units (TGU) as well as hardware digital processing units for local test result processing or parameter extraction. The TMU channels rely on a component-invariant vernier-delay measurement circuit and the TGU channels rely on linear programmable delay circuitry. The system supports both LVDS and CML highspeed digital interface standards at rates of up to 5 Gbps. This solution occupies 3"/spl times/4" of board area, which makes it suitable for placement on the DUT-board. It has a relative delay generation resolution of 3 ps at 5 Gbps, and is capable of autonomous, platform-independent pass-fail testing.

Flash time-to-digital converters (TDCs) are well-suited for use in on-chip timing measurement systems because they can be operated at high speeds, offer low test time, and are relatively easy to integrate. However, clock jitter in modern integrated circuits is often on the same order of magnitude as the temporal resolution of the TDC itself. Therefore, techniques are required to increase the resolution of these devices, while ensuring timing accuracy. This work presents a high-resolution flash TDC that exploits the random offsets on flip-flops or arbiters to perform time quantization. It also describes a novel technique based on additive temporal noise to accurately calibrate the measurement device. Simulation and experimental results reveal that the latter method can calibrate the high-resolution flash TDC down to 5 ps within reasonable error limits. In addition, accurate timing measurement of jitter below 14 ps has been experimentally validated using a high-resolution flash TDC fabricated in a 0.18-/spl mu/m CMOS process.

Noise, especially clock jitter effects, in a DSP-based mixed-signal test system severely limits its measurement accuracy. This is especially acute in high-frequency sampling systems. This work illustrates an efficient method to improve measurement accuracy and precision by reducing the uncertainty of a DSP-based measurement without an increase in test time. A new digitizer architecture is introduced. The digitizer was fabricated in a 0.18 /spl mu/m CMOS process. Experimental results were obtained validating the proposed technique.

Jitter characterization has become significantly more important for systems running at multigigahertz data rates. Time and frequency domain characterization of jitter is thus a crucial element for system specification testing. Time domain jitter measurement on a data signal with subgate timing resolution can be achieved using two delay chains feeding into the clock and datalines of a series of D-latches known as a Vernier delay line (VDL). An important drawback to the VDL structure is that its measurement accuracy depends on the matching of the various delay elements. Although careful layout techniques can help to minimize these mismatches, it cannot eliminate them completely. As well, due to the nature of the design, a relatively large silicon area is required for silicon implementation. In this paper, a novel technique is developed which reduces the silicon area requirements by two orders of magnitude, as well enables the measurement device to be synthesized from a register transfer level (RTL) description. A custom IC was designed and fabricated in a 0.18-/spl mu/m CMOS process as a first proof of concept. The design requires a silicon area of 0.12 mm/sup 2/ and measured results indicate a timing resolution of 19 ps. The synthesizable nature of the design is demonstrated using an field-programmable gate-array implementation. As test time is an important consideration for a production test, an extension to the component-invariant VDL technique is provided that reduces test time at the expense of more hardware. Finally, a method for obtaining the frequency domain characteristics of the jitter using the VDL will also be given.

The simultaneous operation of multiple embedded analog test cores is investigated through experiments on a prototype integrated circuit containing eight such cores. Each core consists of a scan memory, some passive filters, and a fully synchronized integrated waveform digitizer for signal extraction. The circuit supports fully differential signal generation and digitization and employs common circuit techniques to enhance robustness to process variation. Simultaneous operation is demonstrated to achieve over 12-bits of amplitude resolution and more than 70 dB SFDR over a 20 MHz bandwidth. Matching issues are investigated, and instrument uniformity across about 250 cores is verified by measuring waveform generator offset errors, digitizer offset errors, and test core frequency response variability.

Summary form only given. Embedded test is essential for many of today's high-speed electronic designs that involve state-of-the-art silicon processes. Attempting to perform timing and frequency measurements across the chip I/O is fraught with parasitic interconnect issues, leading to excessive noise pick-up, asymmetrical delays and uneven incident/reflection levels. Interestingly enough, the problem of on-chip interconnects is a well-recognized problem in many VLSI-related conferences. Packing such large numbers of interconnects in such a small volume leads to numerous coupling and cross-talk phenomena that are limiting the performance of advanced circuit designs. The problem associated with moving large volumes of data across the chip interface during the test phase seems to have gained less interest at leading conferences when in fact the problem is quite similar, if not worse. As the number of chip I/Os increase, the separation distance and conductor thickness is being forced to decrease, leaving only the length and material properties of the interconnect under our control. Changing the material properties of the interconnect is a steady endeavor and will less likely result in any radical improvement, leaving us with only the length of the interconnect under our direct control. At the present time, the tester-DUT interconnect length is on the order of 10 cm-100 cm, limiting the interconnect bandwidth to, at most, a few GHz. To measure signals with bandwidths beyond this limit, the tester electronics MUST be brought closer to the DUT, or even better, directly on-chip. Hence, BIST or some other form of embedded test will be a fact, it just a matter of time.

In recent years, much effort has been placed on improving the performance of timing and jitter measurement devices using Delay Locked Loop (DLL) and Vernier Delay Line (VDL) techniques. However, these approaches require highly matched elements in order to reduce differential nonlinearity timing errors. In an attempt to reduce the requirement on element matching, a component-invariant VDL technique is proposed that will enable the measurement device to be synthesized from a register transfer level (RTL) description. Furthermore, as test time is an important consideration during a production test, a method is provided that reduces test time at the expense of more hardware. Experimental results on an FPGA implementation are provided as proof of concept. An IC prototype has also been designed and submitted for fabrication. Implementation details are provided in this paper.

An area efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator. It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement). A prototype IC was fabricated in a 3.3 V 0.35 /spl mu/m CMOS process. It was demonstrated to perform various curve tracing, timing, and spectrum analysis tasks at a sampling frequency of 20 MHz (which was only limited by our experimental setup) while taking up an area equivalent to only about five thousand standard-cell 2-input NAND gates.

A new CMOS differential latched comparator suitable for low voltage, low-power application is presented. The circuit consists of constant-gm rail-to-rail common-mode operational transconductance amplifier followed by a regenerative latch in a track and latch configuration to achieve a relatively constant delay. The use of a track and latch minimizes the total number of gain stages required for a given resolution. Potential offset from the constant-g/sub m/ differential input stage, estimated as the main source of offset, can be minimized by proper choice of transistors sizes. Simulation results show that the circuit requires less than 86 /spl mu/A with a supply voltage of 1.65 V in a standard CMOS 0.18 /spl mu/m digital process. The average delay is less than 1 ns and is approximately independent of the common-mode input voltage.

An efficient technique for generating accurate on-chip DC reference voltages is presented. The technique is based on filtering a digital pulse-modulated sequence in order to extract its average (DC) value. Simplicity is achieved by using a passive on-chip filter and by using an all-digital implementation of the modulator. Moreover, in addition to using pulse-width modulation to encode the value of the output DC level, we propose the use of pulse-density modulation as a more viable technique. The latter has the advantage of using a significantly smaller filter, which translates into a smaller implementation area and a faster settling time. The technique was successfully demonstrated using a prototype IC in a 0.35 /spl mu/m CMOS process.

An area efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator. It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement). A prototype IC was fabricated in a 3.3 V 0.35 /spl mu/m CMOS process. It was demonstrated to perform various curve tracing, timing, and spectrum analysis tasks at a sampling frequency of 20 MHz (which was only limited by our experimental setup) while taking up an area equivalent to only about five thousand standard-cell 2-input NAND gates.

This paper describes a new method to increase the performance of existing arbitrary waveform generators. By encoding the digital words using sigma-delta techniques, it is possible, with the simple addition of an analog filter, to decrease the noise floor in a narrow band while keeping the same memory requirements. Calibration techniques to deal with the non-idealities of the arbitrary waveform generator are also presented and verified experimentally.

A multiple pass A/D conversion technique is proposed for mixed-signal test applications. Only a single on-chip comparator and sample-and-hold circuit is required to digitize repetitive analog waveforms. Simulations show 10 bits of amplitude resolution at 300 MHz for a bipolar comparator design (0.8 /spl mu/m BiCMOS process), and 10 bits of amplitude resolution at 667 MHz for a CMOS comparator design (0.5 /spl mu/m CMOS process). A prototype IC designed for a 0.5 /spl mu/m CMOS process has been sent for fabrication. Experimental results from a prototype board (implemented with discrete components) are given.

This paper addresses the issue of the stimulation of charge-pump phase-locked loops for built-in self-test applications. It is shown that three nodes of the PLL qualify for test signal injection. The hardware and methodology for each are discussed. In particular, a comprehensive explanation of the use of delta-sigma modulation in the time domain is provided. Furthermore, implementation issues of analog tests with signal generation based on coarse quantization are discussed. The effects of the quantization noise arising from delta-sigma modulation on the dynamic range of phase-locked loop nodes is evaluated. Original experimental results validate one of the method which was not verified previously. In conclusion, the strengths and weakness of each of the three methods for phase-locked loop stimulation are highlighted.

This paper describes a new method to generate analog signals with high precision at very low hardware complexity. This method consists in reproducing periodically a recorded portion of the bitstream output of a sigma-delta modulate. This technique utilizes less hardware than conventional frequency synthesis methods and does not require a multi-bit DAC. However when a multi-bit DAC is already available, the technique can be used to increase the quality of the signal in the frequency band of interest using existing hardware. The paper demonstrates how this method can be used to generate signals for Built-in Self-Test and standard Analog and Mixed-Signal Test. Experimental results illustrating the design simplicity and low overhead are given.

An all-digital technique for the measurement of the jitter transfer function of charge-pump phase-locked loops is introduced. Input jitter may be generated using one of two methods. Both rely on delta-sigma modulation to shape the unavoidable quantization noise to high frequencies. This noise is filtered by the lowpass characteristic of the device and has a minimal impact on the test results. For response measurement, the output jitter is compared against a threshold. As the stimulus generation and output analysis circuits are digital and do not require calibration, this jitter transfer function measurement scheme is highly amenable to built-in self-test. The technique can also be used to adaptively tune a PLL after fabrication. The validity of the scheme was verified experimentally with off-the-shelf components.

This paper presents a tutorial on mixed-signal testing. Our focus is on testing the analog portion of the mixed-signal device, as the digital portion is handled in the usual way. We begin by first outlining the role of test in a manufacturing environment, and its impact on product cost and quality. We look at the impact of manufacturing defects on the behavior of digital and analog circuits. Subsequently, we argue that analog circuits require very different test methods than those presently used to test digital circuits. We then describe four common analog test methods and their measurement setups. We also describe how analog testing can be accomplished using digital sampling techniques. Finally, we close this tutorial with a brief description of several developments presently underway on the design of testable mixed-signal circuits.

One method for the testing of mixed analog/digital integrated circuits involves the digital encoding of analog signals into an aperiodic pulse-density-modulated (PDM) serial bit stream and using it to stimulate a device under test. This paper describes a method for obtaining a short periodic approximation of the PDM pattern and identifies two methods of integrating this analog test scheme into the current digital test environment: RAM- and scan-based storage. Using such design-for-test logic as the 1149.1-1990 JTAG architecture and a typical RAMBIST controller these analog signal generation techniques can be added to digital ICs with minimal additional hardware overhead.

A design method is proposed for the synthesis of linear, high-order, continuous-time filters using a unique translinear integrator circuit. Unlike previous attempts at incorporating translinear circuits into filter design, the proposed theory makes explicit use of the exponential nature of the bipolar transistor. This technique is based on the operational simulation of LC ladders. A 5th-order Chebyshev filter is designed, simulated and verified experimentally. The filter shows good amplitude response as well as distortion levels comparable to other filtering schemes.

This paper presents an analysis technique that can be used to compute the harmonic and intermodulation distortion levels of a sampled-data circuit directly from a SPICE transient analysis. It is useful for analyzing the nonlinear behavior of switched-capacitor and switched-current circuits at the transistor level. The approach is valid for all input signal levels, makes no assumption of the underlying nonlinearity, and its accuracy is limited only by the numerical accuracy of SPICE.

An analog sine wave generator based on a digital resonator and a bandpass delta-sigma (/spl Delta//spl Sigma/) modulator is presented. Except for a 1-bit D/A, this design is entirely digital allowing precise control over the amplitude and frequency of oscillation. Furthermore, it is area efficient as it does not require a ROM or a multiplier. Unlike previous designs, this circuit is capable of operating at any ratio of the clock frequency. We envision that this device will be used in communications circuits or as a test stimulus for mixed-signal ICs.

This paper presents significant improvements in the generation of analog signals for on-chip analog circuit testing. In particular the novel oscillators proposed here can achieve signal-to-noise ratios far greater than previous designs, while remaining area-efficient. One particular example illustrates a 30 dB improvement in the SNR. Alternatively, signals can be generated with the same SNR as with older designs but over a wider range of frequencies. Multitone signal generation is enhanced in the same fashion. Prototypes were built and satisfactorily tested on FPGA technology.

The price of an increasing number of mixed-signal devices is presently being dominated by the cost of performing production testing. Probably the two most important factors affecting this cost are the direct cost of the test equipment and the time that a device-under-test (DUT) spends on that equipment. Another factor is the indirect cost incurred when test development time becomes the critical step in the manufacture of new devices. The cost of mixed-signal testers is exceedingly high on account of their requirement for both digital and analog test equipment with very high-performance capabilities. Moreover, the time the device spends on these testers can be on the order of minutes. The author discusses the problems outlined and makes some recommendations for the test community at large.

Wireless communication is a rapidly expanding field and considerable research effort is underway. Electronic system manufacturers are actively trying to incorporate all of the RF, IF and baseband functions on the fewest possible ICs so as to reduce system size and cost, and to improve overall system performance. Unfortunately, without a coherent test strategy, any cost reduction gained by miniaturization will be offset by increased testing costs. In this work we propose a built-in self-test scheme for bandpass type systems such as those used in wireless communication devices. The scheme is centered around a high frequency oscillator based on bandpass delta-sigma modulation techniques and a digital extraction method. We will show through experiments that measures meaningful to the analog test engineer such as signal-to-noise ratio, frequency response and intermodulation distortion are obtainable with this method.

VAMP (Variation Analysis with Matching Program) considers the impact on system-level performance caused by device-level parameter variations and mismatch effects using hierarchical behavioral modelling and statistical circuit simulation. It targets cases for which complete transistor simulation is not feasible. Hierarchy is used to decrease model dimensionality and reduce the intensive simulation requirements. Approximation of distributions at an intermediate level is the key to making the link between the detailed device level and the abstract system level tractable, both in terms of clarity and of computing load.>

The Switched-Current (SI) technique is a circuit method that enables analog sampled-data circuits to be realized with a standard digital CMOS process. At this time it is fair to say that SI circuits are realized from either first- or second-generation type current memory cells, with the latter cell being favored owing to its perceived better sensitivity behavior. Unfortunately, however, the second-generation current memory cell has some serious circuit drawbacks. These include large internal transient glitches that cause large linear and nonlinear circuit errors, as well, requires a more complicated circuit. When all factors are considered including the sensitivity issue, it is our opinion that the first-generation cell is superior to the second-generation memory cell. In this paper we shall present our arguments and experiments that back up these claims.>

This paper presents the design of an analog oscillator capable of generating multi-tone signals by encoding the information in an oversampled delta-sigma modulated bit-stream. With the exception of an imprecise lowpass filter, the proposed design is completely digital allowing accurate control of the amplitude, frequency, and phase of all sinusoids making up the multi-tone signal. Simulations and FPGA experiments performed to date have verified the performance of the proposed design which is envisioned to open new directions in the mixed analog/digital testing field.

Built-in-self-test (BIST) for VLSI systems is desirable for production-time testing and in the field diagnostics. This paper discusses a Mixed Analog Digital BIST (MADBIST) for a frequency response test and an intermodulation distortion test of an Analog-to-Digital converter. The MADBIST strategy for the FR and IMD tests of the ADC is introduced, accuracy issues are discussed, and preliminary experimental results are presented.>

Built-In-Self-Test (BIST) for VLSI systems is desirable in order to reduce the cost per chip of production-time testing by the manufacturer. In addition, it can provide the means to perform in-the-field diagnostics. This paper discusses a mixed analog-digital BIST (MADBIST) for a signal-to-noise-ratio test of an analog-to-digital converter. The MAD-BIST strategy for the SNR test of the A/D converter is introduced, accuracy issues are discussed, and experimental results are presented.>