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Kai-Ming Chan

dblp:02/2653 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2004
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 50% Memory systems · 50%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache
0.012004
Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform · ASPLOS 2004
Processor architecture and microarchitecture › multithreading
helper threads
0.012004
Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform · ASPLOS 2004
Processor architecture and microarchitecture
multithreading
0.012004
Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform · ASPLOS 2004
Memory systems › cache
prefetching
0.012004
Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform · ASPLOS 2004
Compilers and program optimization
register allocation
0.012004
Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform · ASPLOS 2004

Methods — techniques the papers use, named apart from their topics

user-level multithreading · 0.1prefetching · 0.1
YearPublicationVenuePosition
2004 Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform
abstract
Helper threading is a technology to accelerate a program by exploiting a processor's multithreading capability to run ``assist'' threads. Previous experiments on hyper-threaded processors have demonstrated significant speedups by using helper threads to prefetch hard-to-predict delinquent data accesses. In order to apply this technique to processors that do not have built-in hardware support for multithreading, we introduce virtual multithreading (VMT), a novel form of switch-on-event user-level multithreading, capable of fly-weight multiplexing of event-driven thread executions on a single processor without additional operating system support. The compiler plays a key role in minimizing synchronization cost by judiciously partitioning register usage among the user-level threads. The VMT approach makes it possible to launch dynamic helper thread instances in response to long-latency cache miss events, and to run helper threads in the shadow of cache misses when the main thread would be otherwise stalled.The concept of VMT is prototyped on an Itanium ® 2 processor using features provided by the Processor Abstraction Layer (PAL) firmware mechanism already present in currently shipping processors. On a 4-way MP physical system equipped with VMT-enabled Itanium 2 processors, helper threading via the VMT mechanism can achieve significant performance gains for a diverse set of real-world workloads, ranging from single-threaded workstation benchmarks to heavily multithreaded large scale decision support systems (DSS) using the IBM DB2 Universal Database. We measure a wall-clock speedup of 5.8% to 38.5% for the workstation benchmarks, and 5.0% to 12.7% on various queries in the DSS workload.
Perry H. Wang, Jamison D. Collins, Hong Wang 0003, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen
ASPLOS6