Modern telecommunications networks maintain synchronization and distribute accurate timing information using approaches with strict requirements on clock quality and jitter and wander at interfaces. In the future, packet networks may be used for timing distribution and synchronization e.g. using IEEE 1588v2 specifying the Precision Time Protocol (PTP). Without amelioration, there may be effects on data buffers within telecommunications networks which have been designed with particular assumptions of clock quality. Applications such as digital audio and video also have synchronization requirements and limits on jitter and wander tolerance. Attention is needed on the impact of clock quality due to clock synchronization on the synchronization and jitter and wander limits for data services over networks. A well-understood approach to the transfer of timing for a data service over a packet network is the Synchronous Residual Time Stamp (SRTS) method. We previously presented a novel approach to modelling and visualising jitter spectra in SRTS timing transfer due to jitter in the reference clocks. In this paper, we present experimental results, which validate the appropriateness of our approximations. Experimental results also show the existence of some spectral components not predicted from the modelling. In the paper we discuss the origins of these spectral components.

Particle swarm has proven to be competitive to other evolutionary algorithms in the field of optimization, and in many cases enables a faster convergence to the ideal solution. However, like any optimization algorithm it seems to have difficulties handling optimization problems of high dimension. Here we first show that dimensionality is really a problem for the classical particle swarm algorithms. We then show that increasing the swarm size can be necessary to handle problem of high dimensions but is not enough. We also show that the issue of scalability occurs more quickly on some functions.

When dealing with complex optimisations problems, evolutionary computation techniques have proven to be very helpful. Amongst optimisation algorithms driven by evolutionary computation techniques, particle swarm algorithms have proven to be a very good alternative to genetic algorithms because of their faster convergence. However they can still suffer from premature convergence to local optima. Premature convergence occurs when the particles of the swarm are too close to each other to enable further exploration of the space. To put it another way, the dispersion or distribution of the swarm throughout the search space has been localised to a small region with a consequent stagnation of the search process. Many strategies have been used to try to prevent convergence to a local optimum. However little work

In constant bit-rate timing transfer, the reference clocks which encode and reconstruct the service clock at origin and destination may be jittered. We present new, straightforward approaches to finding and visualizing jitter spectra in timing transfer for jittered destination and reference clocks, and confirm our results by simulation

We characterize the metastability measurement system (Dike, 1999) in which asynchronous data input and sampling clock frequencies trigger metastability. We develop the equation describing the time interval between data and clock inputs for practical frequencies and show that it takes on discrete values in the absence of jitter and that the presence of jitter perturbs these discrete values. Finally, we present experimental results supporting our characterization

The synchronous residual time stamp (SRTS) is widely implemented for the transport of the service clock associated with continuous bit-rate services in asynchronous transfer mode adaptation layer 1. We present a new approach to service clock regeneration, which is simple to implement and can be proven to be correct.

The synchronous residual time stamp (SRTS) is one approach approved for the encoding and transporting of the continuous bit rate (CBR) service clock in ATM Adaptation Layer 1 (AAL1) allowing CBR services to be transported in ATM cells over the B ISDN. It has been shown by the authors and others that the SRTS method generates waiting time jitter analogous to that produced by other synchronization processes such as pulse stuffing synchronization. Modeling of the synchronization process as it applies to the SRTS method requires a time domain approach to produce an exact expression of the jitter. In this paper, we apply a new time domain analysis technique previously developed by the authors to derive the expressions for the jitter spectrum of the synchronization process in the presence of input jitter on the service clock. Furthermore, the particular form taken by the jitter spectrum when the input jitter is sinusoidal is also found. Experiments verifying the synchronization process jitter spectrum, both with and without sinusoidal input jitter, are reported. Confirmation is also provided that it is possible to approximate timing jitter by phase jitter as long as certain frequency-amplitude limits are observed.

The synchronous residual time stamp (SRTS) method has been recommended by the ITU-T as one approach to the transfer of timing information for continuous bit rate (CBR) services being carried by the asynchronous transfer mode (ATM) adaptation layer 1 (AAL1) of the broadband integrated services digital network (B-ISDN). We give an overview of the SRTS method including a description of service clock recovery at the destination. On the basis of analytical expressions derived, we show that even in an ideal SRTS system, where all clocks are jitter-free, the SRTS method inherently generates jitter. We also show that this jitter is equivalent to the so-called waiting time jitter that is found in conventional timing justification techniques. In other systems where waiting time jitter is generated, parameters are chosen in order to minimize the amount of waiting time jitter produced and in which part of the spectrum it is located. We show that for the SRTS method, the choice of parameters to minimize waiting time jitter is quite restricted. For higher service clock frequencies and clocks with large tolerances, it may be impossible to choose parameters to influence the characteristics of the waiting time jitter produced.

A new synchronizer design is presented. Current synchronizer designs have certain disadvantages, both in characterization and in the tradeoff between settling time and sampling rate, which are overcome in the new design. Two possible implementations of the synchronizer are discussed.

The jitter generated by two different approaches to synchronization of an external timing source is analyzed. The two approaches are: the use of conventional stuffing and the use of a simpler frame sampling synchronizer. It is shown that these two approaches have the same jitter power density spectrum. The result is obtained using a new time domain method developed in the paper. Exact expressions for the jitter on the synchronized external timing source are obtained. Furthermore, the effect of quantization in the conventional stuffing synchronizer on the jitter expressions obtained is also explored. Jitter generated by the frame sampling synchronizer is also analyzed using the time domain method, which again produces an exact expression. In the case where certain parameters of the two approaches are related, the location of spectral lines in their respective jitter spectra is shown to be identical. It is also shown that both approaches to synchronization introduce the so-called waiting-time jitter.

This paper proposes a new design for a frame sampling synchronizer and gives some typical applications for the device. It also discusses metastability which arises in the system due to the existence of asynchronous inputs. The motivation for the new design, details of the design and its modelling are also covered. Finally the jitter generated by the synchronizer is analysed.>