Superscalar implementations of RISC architectures are emerging as the dominant high-performance microprocessor technology for the mid-1990's. For instruction-level parallelism to increase beyond present levels, multiple memory operations per cycle are required. The paper evaluates several alternatives for two-ported data cache memory systems. A new split data cache memory design is compared to a more conventional true dual-ported memory. Experimental simulations are used to determine the performance benefits of these cache models on superscalar processors. These experiments are reported for a contemporary processor with modest instruction-level parallelism and for a hypothetical very aggressive, highly parallel processor.>