Surya Veeraraghavan

dblp:02/3587 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1988
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 70% Integrated circuit design · 30%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
circuit simulation
0.021988
Model selection for SOI MOSFET circuit simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988
SPICE Simulation of SOI MOSFET Integrated Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1986
Electronic design automation › circuit simulation › analog circuit simulation
SPICE simulation
0.011986
SPICE Simulation of SOI MOSFET Integrated Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1986
Integrated circuit design
semiconductor device modeling
0.011988
Model selection for SOI MOSFET circuit simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1988

Methods — techniques the papers use, named apart from their topics

current-voltage characteristic analysis · 0.0user-defined controlled sources · 0.0charge-based device modeling · 0.0
YearPublicationVenuePosition
1988 Model selection for SOI MOSFET circuit simulation
abstract
A method for experimentally selecting proper silicon-on-insulator MOSFET models for circuit simulation is described, verified, and demonstrated. The selection criteria are derived from steady-state current-voltage characteristics predicted by thin-film and (semi-)bulk models. The necessity for proper model selection is emphasized by revealing significant simulation errors that result from seemingly valid but actually empirical models.>
Jerry G. Fossum, Surya Veeraraghavan, Dan Fitzpatrick
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
1986 SPICE Simulation of SOI MOSFET Integrated Circuits
abstract
A five-terminal, charge-based model for the thin-film silicon-on-insulator (SOI) MOSFET is implemented in SPICE2, thereby enabling, for the first time, proper simulation and CAD of SOI MOS integrated circuits in which the unique floating-body and back-gate-bias effects can be significant. The implementation is achieved, without having to rewrite the circuit simulator, by developing a general method for incorporating new charge-based device models into SPICE2 that utilizes user-defined controlled sources (UDCS's). The utility and computing efficiency of the SOI MOSFET model implementation are demonstrated by simulating several representative SOI MOS circuits.
Surya Veeraraghavan, Jerry G. Fossum, William R. Eisenstadt
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1