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Shigenobu Suzuki

dblp:02/4080 · DBLP profile ↗
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4ranked-venue papers
2as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 93% Integrated circuit design · 5% High-performance computing · 2%

Topics — the 10 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
logic synthesis
0.021991
Timing Optimization on Mapped Circuits · DAC 1991
TRIP: An Automated Technology Mapping System · DAC 1987
Electronic design automation › physical design
timing optimization
0.011991
Timing Optimization on Mapped Circuits · DAC 1991
Electronic design automation › physical design
layout optimization
0.011987
TRIP: An Automated Technology Mapping System · DAC 1987
Electronic design automation
physical design
0.011987
TRIP: An Automated Technology Mapping System · DAC 1987
Electronic design automation › logic synthesis
technology mapping
0.011987
TRIP: An Automated Technology Mapping System · DAC 1987
Electronic design automation › design methodology
technology migration
0.011987
TRIP: An Automated Technology Mapping System · DAC 1987
Electronic design automation
design flow
0.011985
Integrated design system for supercomputer SX-1/SX-2 · DAC 1985
Electronic design automation › hardware verification and test
hardware verification
0.011985
Integrated design system for supercomputer SX-1/SX-2 · DAC 1985
Integrated circuit design
digital circuit design
0.011991
Timing Optimization on Mapped Circuits · DAC 1991
High-performance computing
supercomputer architecture
0.011985
Integrated design system for supercomputer SX-1/SX-2 · DAC 1985

Methods — techniques the papers use, named apart from their topics

timing optimization · 0.0rule base · 0.0partitioning · 0.0CAD tools · 0.0
YearPublicationVenuePosition
1991 Timing Optimization on Mapped Circuits
abstract
Article Free Access Share on Timing optimization on mapped circuits Authors: Ko Yoshikawa NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, Japan NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, JapanView Profile , Hiroshi Ichiryu NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, Japan NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, JapanView Profile , Hisato Tanishita NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, Japan NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, JapanView Profile , Sigenobu Suzuki NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, Japan NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, JapanView Profile , Nobuyoshi Nomizu NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, Japan NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, JapanView Profile , Akira Kondoh NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, Japan and NEC Engineering Corp. NEC Corporation, 1-10 Nisshin-cho, Fuchu-city, Tokyo, Japan and NEC Engineering Corp.View Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 112–117https://doi.org/10.1145/127601.127639Published:01 June 1991Publication History 17citation216DownloadsMetricsTotal Citations17Total Downloads216Last 12 Months12Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF
Ko Yoshikawa, Hiroshi Ichiryu, Hisato Tanishita, Shigenobu Suzuki, Nobuyoshi Nomizu, Akira Kondoh
DAC4
1990 A Framework Environment for Logic Design Support System
abstract
A framework for an integrated logic design support system is presented. Owing to the use of this framework, it is easy to develop and add commands which have variable functions for automated logic design. ILOS (integrated logic design system) has been developed using this framework. ILOS supports various design styles because these commands are flexibly combined in the framework. These commands are hierarchical circuit conversion, distributor synthesis, partitioned hierarchical design support, generation of schematic diagrams and logic synthesis, ILOS is used in the design of supercomputers, large-scale computers and medium-scale computers. In large-scale computer design, ILOS reduced manpower costs by 70%.>
Kaname Kuroki, Nobuyoshi Nomizu, Shigenobu Suzuki, Kazutoshi Takahashi
ICCAD3
1987 TRIP: An Automated Technology Mapping System
abstract
A technology mapping system, used for computer design in NEC, is presented. The features of this system are technology conversion and logical/physical optimization, based on a rule base, partitioning support, conversion verification and special layout consideration. This system is practically used for many applications for technology mapping, including redesigning an existing total unit into a new unit, based on up-to-date LSI technology. The resulting effect is quick inputting of integrated circuit technology progress into practical computer design area.
Shigenobu Suzuki, Tatsushige Bitoh, Masao Kakimoto, Kazutoshi Takahashi, Takao Sugimoto
DAC1
1985 Integrated design system for supercomputer SX-1/SX-2
abstract
An integrated design system using CAD tools, which was applied to the design of the supercomputer (SX-1, SX-2), is described. The key points for designing the large system are a short design cycle, high productivity, high quality and user-friendly interface to the CAD system. Three strategies have been adopted: engineering work station utilization, thorough verification in an early design stage and establishment of a design flow using CAD tools. By the CAD system based on those strategies, a supercomputer with high quality was successfully designed in a short time.
Shigenobu Suzuki, Kazutoshi Takahashi, Takao Sugimoto, Mikio Kuwata
DAC1