Accurate tissue tracking and dense reconstruction in endoscopic procedures present fundamental challenges, particularly when addressing complex tissue deformations captured by monocular cameras. Most existing approaches compromise between dynamic tracking accuracy and reconstruction density due to the ill-posed nature of monocular deformable scene re-construction. In this paper, we introduce EndoSD-SLAM, a real-time dense monocular SLAM framework designed for deformable endoscopic scenes that simultaneously achieves precise tracking and high-fidelity dense reconstruction. Our approach leverages a novel hybrid representation: (1) a sparse deformable keypoint map with visco-elastic constraints that enables robust camera tracking under tissue motion, and (2) a dense 3D Gaussian splatting map optimized through differentiable rendering for photorealistic reconstruction. To seamlessly integrate these com-plementary representations, we propose a depth alignment mod-ule that establishes constraints between sparse geometric priors and dense rendering, eliminating the dependency on external depth sensors while maintaining geometric consistency and scale accuracy. Extensive experiments on both synthetic (C3VD) and real-world (EndoMapper, StereoMIS) datasets demonstrate that EndoSD-SLAM significantly outperforms existing methods in reconstruction quality while maintaining real-time performance, showcasing its potential for enhanced intraoperative visualization and surgical guidance. The code will be released soon.

The main contribution of this work is to propose an efficient parallel prefix sums architecture based on the recently-developed technique of shift switching with domino logic, where the charge/discharge signals propagate along the switch chain producing semaphores in a network that is fast and highly hardware-compact. The proposed architecture for computing the prefix sums of N-1 bits features a total delay of (4 log N + /spl radic/N-2)/sub */T/sub d/, where T/sub d/ is the delay for charging or discharging a row of two prefix sum units of eight shift switches. Our simulation results show that, under 0.8-micron CMOS technology, the delay T/sub d/ does not exceed 1 ns. As it turns out, our design is faster than any design known to us for values on N in the range 1 /spl les/ N /spl les/ 2/sup 10/. Yet, another important and novel feature of the proposed architecture is that it requires very simple controls, partially driven by the semaphores. This significantly reduces the hardware complexity of the design and fully utilizes the inherent speed of the process.

A novel self-repairable and reconfigurable inner-product processor with low-power, fast CMOS circuits and DFT techniques is presented. It takes the advantage of recently proposed decomposition based arithmetic circuit design approach for simple implementation of the reconfigurations, component replacements, and high-quality tests.The processor can be dynamically reconfigured for two types operations: 4 x 8 x 8-b inner product computation and 16 x 16-b multiplication. The self-repair is provided by choosing a fault-free one from 17 possible architectures during the test, which covers more than 52% transistors for the specified faults. Only one extra bit is needed for all reconfigurations, repairs, and tests. The proposed exhaustive DFT technique greatly reduces the test vector length, from 17*232 to 1.5*213, which is as short as that required by the pseudo-exhaustive DFT method recently reported in literature.

multiplier can be directly reconfigured to produce an A novel run-time reconfiguable array of multipliers array of the products in four different input forms. architecture is presented. The processor can be For example, it can produce an array of 64 16-bit easily reconfigured to trade bitwidth for array size, items (products) in 1 pipeline cycle, an array of 16 thus maximizing the utilization of available 32-bit products in 2 pipeline cycles, an array of 4 hardware.

This paper presents a novel approach for low-power high-performance inner product processor design. The processor is dynamically reconfigurable for computing inner products of input arrays with four or more combinations of array dimensions and precision. The processor mainly consists of an array of 8/spl times/8 or 4/spl times/4 small multipliers plus two or three arrays of adders. It requires very simple reconfigurable components. The whole network may be reconfigured by using a few control bits for the desired computations, and the reconfiguration can be done dynamically. The design is regular, modular, and can easily be pipelined, and most parts of the network are symmetric and repeatable. A set of low-power high-performance parallel counters is also proposed for the implementation of the design, which could lead to a significant reduction in worst case power dissipation compared with traditional binary-logic based architectures, while showing superiority in speed, VLSI area, and layout simplicity.

We address the problem of designing efficient and scalable hardware-algorithms for computing the sum and prefix sums of a w/sup k/-bit, (k/spl ges/2), sequence using as basic building blocks linear arrays of at most w/sup 2/ shift switches, where w is a small power of 2. An immediate consequence of this feature is that in our designs broadcasts are limited to buses of length at most w/sup 2/. We adopt a VLSI delay model where the "length" of a bus is proportional with the number of devices on the bus. We begin by discussing a hardware-algorithm that computes the sum of a w/sup k/-bit binary sequence in the time of 2k-2 broadcasts, while the corresponding prefix sums can be computed in the time of 3k-4 broadcasts. Quite remarkably, in spite of the fact that our hardware-algorithm uses only linear arrays of size at most w/sup 2/, the total number of broadcasts involved is less than three times the number required by an "ideal" design. We then go on to propose a second hardware-algorithm, operating in pipelined fashion, that computes the sum of a kw/sup 2/-bit binary sequence in the time of 3k+[log/sub w/ k]=3 broadcasts. Using this design, the corresponding prefix sums can be computed in the time of 4k+[log/sub w/ k]-5 broadcasts.

The first main contribution of this work is to propose an efficient VLSI architecture obtained by augmenting the Mesh with Multiple Broadcasting (MMB) with precharged 1-bit row and column buses. The new architecture, which we call Mesh with Hybrid Buses (MHB for short), is realizable in VLSI with no increase in the area or the wiring complexity of the MMB chip. Our second main contribution is to show that the MHB is extremely well-suited for solving an entire slew of digital geometry tasks. The MHB is not a reconfigurable architecture. Yet, quite remarkably, for a large number of fundamental digital geometry tasks, the MHB offers a level of performance previously attained only by reconfigurable architectures. Specifically, with a digital image pretiled onto a MHB of size /spl radic/n/spl times//spl radic/n one pixel per processor, we show that the problems of computing the convex hull of the image, computing the diameter and the width of the image, deciding whether a set of digital points is a digital line, computing the maximum distance between two images, deciding whether two images are linearly separable, computing several moments and low-level descriptors of the image, including the perimeter, area, center, and median row of its convex hull, can be solved in O(log n) time. By contrast, the fastest possible algorithms for the problems above on the MMB run in /spl Theta/(n/sup 1/6/) time. Finally, we go on to show that, with minor changes, our algorithms can be implemented to run within cost-optimality on a MHB of size /spl radic/n/log n/spl times//spl radic/n/log n.

This paper presents novel very large scale integration (VLSI) architectures in support of an efficient implementation of Leighton's well-known Columnsort. The designs take advantage of reconfigurable bus architectures enhanced with simple shift switches. Our first main contribution is to show that Columnsort can be partitioned into two components: a hardware scheme involving the task of sorting arrays of small size and a hardware or software scheme that involves simple data movement tasks. Our second main contribution is to demonstrate that the dynamically reconfigurable mesh architecture can be exploited to obtain a small and efficient hardware sorter. The resulting architectures feature high regularity of circuitry, simplicity of control structure, and adaptability. Both theoretical analyses and simulation tests have shown that the proposed VLSI architectures for sorting are superior to existing designs in the context of sorting small and moderate size arrays.

We present novel fast parallel multiplier schemes. In contrast to the full adder binary logic based traditional designs, we use (incomplete) large parallel counters and large shift switch compressors, which are built based on shift switch logic, a logic with shift switches as logic elements performing modulo arithmetic operations on (non-binary) state signals. With the unique feature of shift switch logic our parallel multiplier schemes have shown superiority in speed and in area compactness. This is provided through the use of a stage-reduced partial product reduction network, the efficient signal interconnection and the simplified final carry lookahead adder. Compared to the well-known designs, our approach possesses higher regularity and simplicity on circuit structures, characterized by both the recursive shift switch networks which localize the major part of partial product reduction and the deliberated utilization of uneven arrival signals which minimize the delay of the multipliers.

The task of computing the prefix sums of a binary sequence (BPS, for short) arises frequently in expression evaluation, data and storage compaction, routing, processor assignment, and operating system design. The main goal of this work is to propose an efficient special-purpose architecture for the BPS problem. Our design exploits a novel and elegant idea that allows us to considerably reduce the number of processors of the best-known design. The resulting design is simple and intuitive and scales easily to handle input sequences of various sizes.

We propose to enhance traditional broadcast buses by the addition of a new feature that we call shift switching. We show that on a linear array of processors enhanced with shift switching, the prefix sums of n bits can be computed in [log(n+1)/log w] broadcasts, each over n switches, assuming a global bus of width w. Next our prefix sums algorithm is used in conjunction with broadcasting on short buses to obtain several efficient architectural designs for the following fundamental problems: 1) ranking linked lists, 2) counting the number of 1's in a sequence of n bits, and 3) sorting small sets. We see our main contribution in showing that the new bus feature leads to designs that are both theoretically interesting and practically relevant.>

The main contribution of this work is to show that a number of fundamental digital geometry tasks can be solved fast on a novel VLSI architecture obtained by augmenting the mesh with multiple broadcast architecture (MMB) with precharged 1-bit row and column buses. The new architecture that we call mesh with hybrid buses (MHB) is readily implementable in VLSI with no increase in the area or the wiring complexity of the MMB chip. More importantly, the new architecture affords us an exponential gain in the running time when compared with the MMB. Specifically, with a digital image pretiled onto an MHB of size /spl radic/n/spl times//spl radic/n one pixel per processor we show that the problems of computing the convex hull of the image, computing the diameter and the width of the image, deciding whether two images are linearly separable, computing several moments and low-level descriptors of the image including the perimeter, area, center, and median row of its convex hull can be solved in O(log n) time. The fastest possible algorithms for the problems above on the MMB run in /spl Theta/(n/sup 1/6/).>

Consider arbitrary collections A = a_1,a_2,.. .,a_n of items and Q = q_1,q_2,...,q_m (1 leqslant mn leqslant n) of queries from a totally ordered universe. The multiple rank problem involves computing for every query qi the number of items in A that have a lesser value. Our contribution is to show that the problem at hand can be solved time-optimally on meshes with multiple broadcasting. More specifically, if the collection A is siored in some order one item per processor and if Q is stored one query per processor in the leftmost frac{m} {{sqrt n }} columns of a mesh with multiple broadcasting of size sqrt n x /sqrt n, the corresponding instance of the multiple rank problem can be solved in Theta left( {m^{frac{1} {3}} n^{frac{1} {6}} } right) time. As an application we present a time-optimal algorithm to compute the histogram of a m-level gray image of size sqrt n x sqrt n in Theta left( {m^{frac{1} {3}} n^{frac{1} {6}} } right) time.

The authors propose a novel VLSI sorting network implementing Leighton's column sort. The network is mech-based and modular; it consists of comparison-exchange processing elements (PEs), routing paths, and short broadcast buses. Each bus contains a small number of simple switches that the authors call shift switches. They enhance and simplify the previously proposed shift switching mechanism to obtain an efficient O(1) VLSI-optimal sorting algorithm. From a theoretical perspective, the new approach reduces significantly both the number of PEs (from N/sup 2/ to N/sup 13/9/) and the number of broadcasts from more than 58 bus broadcasts, each over N switches, to at most 16 bus broadcasts, each over N/sup 4/9/ switches. From a practical standpoint, the network features a significant time-performance gain in comparison with the bitonic sorting circuit, especially when multiple smaller size arrays are sorted in parallel.>

Recently it has been noticed that for semigroup computations and for selection, rectangular meshes with multiple broadcasting yield faster algorithms than their square counterparts. The contribution of this paper is to provide yet another example of a fundamental problem for which this phenomenon occurs.