The increasing deployment of AI (artificial intelligence) on edge devices presents major challenges due to strict constraints on computation, memory, energy, and latency. Effective Edge AI systems thus require multi-objective optimization that balances accuracy, hardware efficiency, and reliability. The Horizon Twinning project AIDA4Edge tackles these challenges by developing methods for efficient and reliable AI on resource-constrained platforms. This paper presents key approaches explored within the project, including neural network quantization, hardware-aware neural architecture search, dynamic neural networks, and self-adaptive resilient AI architectures. Finally, these strategies are placed within a broader, biologically inspired paradigm, highlighting neuromorphic computing as a natural continuation of Edge AI efforts toward highly efficient and resilient intelligent systems.

This tutorial addresses the benefits one can take from deploying on-chip lifecycle management (OCLM) to design resilient Systems-in-Package (SiP). Such benefits are based on the massive deployment of on-chip cross-layer, collaborative sensors that are placed in strategic points of the chiplets and interposer, a data wrapper interface & management hub that is responsible to process and store the collected data from the sensors in a way to create an in-mission history of events, and on-chip analytics engine. The sensors can monitor from siliconlevel information (such as transistor aging, power-supply noise activity, electromigration, and transient faults in memory elements) up to system-level transactions in system bus, processor cores and memory IPs (e.g. task scheduling algorithm, and data and instructions fetched in memory). The sensors can be placed on dies on interposer. Furthermore, IEEE and IEC standards can be used to support data monitoring and collection processes. The analytics engine can be implemented based on simple/straightforward data structures such as Look-up Table (LUT) and Content-Addressable Memory (CAM), or be based on advanced Machine Learning/Artificial Intelligence (ML/AI) algorithms such as Dynamic Neural Network (DNN). The ultimate goal is to perform on-chip lifecycle management to trade, in-mission mode, power, performance, reliability and lifespan.

Reliable electronics plays a major role in shaping our daily lives, being a key enabler for critical applications, such as space missions, avionics, automotive, medicine, banking, automated industry, wireless communication networks, etc. However, design of highly reliable electronic systems remains a challenge with the advances in semiconductor technology and increase in integrated circuit (IC) complexity. In this work, we introduce the Horizon Europe Twinning project TWIN-RELECT, aimed at strengthening the scientific expertise in designing reliable integrated circuits. The paper presents the general project concept and objectives, and main directions of the joint research activities. The primary scientific goal is to contribute to the development of novel, more efficient, European Electronic Design Automation (EDA) tool-chain for design of reliable chips.

The growing demand for deployment of Artificial Intelligence (AI) on resource-constrained edge devices has motivated extensive research on the design of efficient edge-compatible AI hardware accelerators. One of the most promising solutions are the self-adaptive AI accelerators, capable of optimizing in real time their performance and energy consumption according to application requirements. This work introduces the EU-funded project Twinning for Excellence in Adaptive Edge Artificial Intelligence (AIDA4Edge), aimed to advance the state-of-the-art in the design of adaptive neural network accelerators for edge applications. The main goal is to develop a novel hybrid self-adaptive neural network architecture combining spiking and artificial neural networks, and supporting runtime adaptation of network functionality, precision and reliability. Furthermore, we aim to enhance the neural network training by incorporating hardware and quantization constraints in an automated tuning engine.

The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

This tutorial summarizes the on-chip infrastructure such as sensors and dedicated HW redundancy under development at IHP Microelectronics. This infrastructure deals with, for instance, detecting single-event upset (SEU) in memory elements and single-event transient (SET) in logic, measuring electronics aging and tracking in-field realtime circuit speed performance degradation during IC lifetime. Furthermore, after manufacturing process, on-chip sensors can also be used to assess silicon for device screening. Ultimately, this infrastructure allows predicting in-flight SEU rate and remaining IC life-span. Dedicated on-chip watchdogs to guarantee mixed-criticality task execution in realtime operating system (RTOS) is further introduced. Embedded systems based on such watchdogs are assumed to be compliant with the ARINC 653 Std. Currently, this on-chip infrastructure is being implemented by IHP in different versions of a RISC-V processor. Such design is based on a CMOS 130nm rad-hard technology also developed at IHP.

Aging of electronics can be caused by various physical mechanisms, including bias temperature instability (BTI), hot carrier injection (HCI), time-dependent dielectric breakdown (TDDB) and electromigration (EM). Aging phenomena may lead to a degradation of performance and reliability of an electronic system, hence limiting its expected lifetime. The goal of this paper is twofold. First, it presents an advanced, miniature design of an aging sensor; second, it shows how this sensor is integrated with a commercial 5 nm FinFET-based SRAM IP core. The sensor is implemented with a small number of logic gates, resulting in negligible overhead in area, power and delay. The sensor is also equipped with power gating capability. Thus, during idle time, the sensor is temporarily disconnected from the power supply lines to prevent aging of its transistors. Experimental results based on extensive SPICE simulations demonstrate that this approach is able to detect even the slight increase in memory response time due to aging much earlier than a functional error is observed at the memory output. This solution enables mission-mode monitoring of memory operation, which is a critical aspect of silicon lifecycle management (SLM) framework.

Resistive Random Access Memories (RRAMs) have been considered for implementing various emerging applications alongside storage. RRAMs offer the opportunity to address the Von Neumann bottleneck making the implementation of In-Memory Computing (IMC) possible. However, the exploration of RRAM potentials depends on being able to guarantee their reliability during lifetime. In this context, this paper investigates the impact of transistor aging on the behavior of 1T1R RRAM cells. A case study composed of an RRAM block, including peripherals, implemented using the 22 nm FDSOI GF technology is adopted. The obtained results indicate that the transistor aging, which was previously widely ignored, can lead to parametric degradation or even catastrophic faults. In addition, the obtained results show that the transistor type used for implementing the 1T1R RRAM cell, core or IO device, and operating temperature play important roles when analysing aging impact.

Electronic systems can be submitted to hostile environments leading to bit-flips or stuck-at faults and, ultimately, a system malfunction or failure. In safety-critical applications, the risks of such events should be managed to prevent injuries or material damage. This paper provides a comprehensive overview of the challenges associated with designing and verifying safe and reliable systems, as well as the potential of the RISC-V architecture in addressing these challenges.We present several state-of-the-art safety and reliability verification techniques in the design phase. These include a highly-automated verification flow, an automated fault injection and analysis tool, and an AI-based fault verification flow. Furthermore, we discuss core hardening and fault mitigation strategies at the design level. We focus on automated SoC hardening using model-driven development and resilient processing based on sensing and prediction for space and avionic applications.By combining these techniques with the inherent flexibility of the RISC-V architecture, designers can develop tailored solutions that balance cost, performance, and fault tolerance to meet the requirements of various safety-critical applications in different safety domains, such as avionics, automotive, and space. The insights and methodologies presented in this paper contribute to the ongoing efforts to improve the dependability of computing systems in safety-critical environments.

Detection and measurement of ionizing radiation is required in a wide range of terrestrial applications, as well as in space missions. For this purpose, special instruments composed of radiation sensors and readout electronics are utilized. As ionizing radiation may affect the operation of electronic systems, radiation hardness is one of the main design requirements for radiation monitoring systems. In this work, we present a concept of a smart multi-sensor radiation monitoring system. The proposed design is based on the results achieved within the framework of EU-funded ELICSIR project. Our solution provides a new perspective on smart radiation monitoring by combining the concepts of self-awareness, self-adaptivity and artificial intelligence. This solution is suitable for applications where long-term autonomous radiation monitoring is required, such as environmental monitoring at terrestrial level or radiation monitoring in space missions.

With the growing use of embedded systems in our daily lives and the increasing electromagnetic noise level in the environment in which these systems are exposed, the need for reliable operation is paramount. In this scenario, this work presents a study on the use of Artificial Neural Networks (ANNs) to perform in-field identification and classification of different types of noise conducted in the integrated circuit (IC) DC power lines according to a specific set of IEC standards. After identification, proactive actions can be taken to guarantee the expected IC robustness. Such actions can be, for instance, slow down IC clock frequency, increasing power supply voltage and/or activating error detection & correction (EDAC) functions during the period the system is operating under such noise exposition. Experimental results demonstrate that the ANN was able to identify and classify different types of conducted noise in power supply lines with a success rate ranging from 70 to 100% within a latency in the order of 995 ns.

The use of wireless sensor networks (WSN) to support critical monitoring applications is becoming a relevant topic of interest. These networks allow a highly flexible approach to data monitoring and, consequently, a major breakthrough for several application domains, from industrial control applications to large building domotics and health care applications. One of the major impairments of using wireless networks to support critical monitoring applications is the electromagnetic noise, which may increase the packet loss ratio to unacceptable values. In this paper, we assess different techniques of cooperative communication and network coding that can be useful to mitigate the aforementioned problem. These techniques may be implemented in WSN nodes in conformance with the IEEE 802.15.4 standard, to reduce the impact of electromagnetic interferences upon the packet loss ratio. In this paper, we report an experimental assessment of the network coding and cooperative diversity techniques, where the network is subjected to a controlled electromagnetic interference inside of an anechoic chamber. The experimental results show that, by using these techniques, it is possible to increase the success rate of communication in typical electromagnetic noisy environments.

Accurate prediction of circuit aging is essential to reliable design, in particular for critical applications. Based on intensive HSPICE electrical simulations, we developed a predictive model to compute NBTI-induced path delay degradation at gate-level. The method is based on a static timing analysis that computes path delay under NBTI-induced VTHp (pMOS transistor threshold voltage) degradation. The proposed approach is demonstrated on an industrial ALU circuit design. The obtained results demonstrate a good fitting between the developed model and HSPICE simulations with several orders of magnitude gain in simulation speed.

This paper proposes an early resilience methodology to identify circuit output nodes where aging sensors should be inserted for an error prediction framework. The methodology is based in a pre-layout statistical estimation of the signal paths likely to become critical due to NBTI and/or Process Variations. To handle the fact that spatial correlation information is not available at early steps of the design flow, a statistical approach maximizing critical paths coverage is proposed. The results obtained with the early prediction methodology are compared with those obtained with spatial correlation information. The proposed methodology provides a good prediction of the set of critical paths to be monitored. Furthermore, location and number of aging sensors required to be inserted at critical paths output nodes are closely predicted.

One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It may increase the switching threshold voltage of pMOS transistors and as a result slow down signal propagation along the paths between flip-flops thus causing functional failures in the circuit. In this paper we propose an approach to identify NBTI-critical paths in nanoscale logic that is based on analyzing combination in different degrees of the three parameters: delay-critical paths, gate input signal probability and the gate fan-out degree along the paths. Further the identified NBTI-critical path can be used e.g. for introduction of aging sensors circuitry, rejuvenation stimuli generation, etc. The proposed approach is demonstrated on an industrial ALU circuit design.

In nanoscale FPGAs, variability and aging significantly limit performance. In this paper, a novel aging monitoring methodology for FPGA-based designs to mitigate those effects is proposed. Local sensors are embedded in the configured functionality, monitoring critical paths, at production or during product lifetime. No design freeze (slice and routing locked) is required. When sensors observe a user's defined time guardband violation, safe operation is endangered and action can be triggered, either to reduce clock frequency or to increase core VDD. Simulation and experimental results are presented, using Spartan 6 boards and vendor tools. The testbench uses a Data Acquisition (DAQ) system with Triple Modular Redundancy (TMR) architecture and a Built-In Self-Test (BIST) infrastructure. It is shown that local sensors will anticipate system failure. Various devices are also used to analyze sensitivity to process variations.

One of the most important phenomena degrading Nano-scale Static Random Access Memory (SRAM) reliability is related to Negative-Bias Temperature Instability (NBTI). This paper presents the integration of the OCAS (On-Chip Aging Sensor) approach in the design methodology of 28nm single-port SRAM cores. The goal is to enhance the current test and repair on-chip infrastructure to detect SRAM aging during system lifetime. OCAS is able to detect the aging state of a cell in the SRAM array. The strategy is based on the connection of one OCAS per SRAM column, which periodically performs off-line testing by monitoring write operations into the SRAM cells to detect aging. The approach is application-transparent since it is does not change the SRAM content after testing. SPICE simulations allowed us to analyze the OCAS sensitivity to detect early aging states in this very deep submicron technology, as well as the area, power and performance penalties due to the sensor insertion.

Today, the increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of a System-on-Chip (SoC). Therefore, SRAM's robustness is considered crucial in order to guarantee the reliability of such SoCs over lifetime. In this context, one of the most important phenomena that degrades Nano-scale SRAMs reliability is related to Negative-Bias Temperature Instability (NBTI), which accelerates memory cells aging. This paper proposes a new approach to detect SRAM aging during system lifetime based on an On-Chip Aging Sensor (OCAS). The OCAS is able to detect any specific aging state of a cell in the SRAM array. The strategy is based on the connection of one OCAS every SRAM column, each periodically performing off-line tests by monitoring the write operations on the SRAM cells in order to detect aging. To prevent the OCAS from aging and from dissipating leakage power, the OCAS circuitry is powered-off during its idle periods. Experimental results demonstrate the sensor's high sensitivity to detect early aging states and therefore, guaranteeing high memory reliability. Finally, the area overhead related to the sensors' insertion is almost negligible.

With the IEC 62.132 proposal, the roadmap for standardization of Electromagnetic (EM) immunity measurement methods has reached a high degree of success. The same understanding can be taken from the MIL-STD-883 H for Total Ionizing Dose (TID) radiation. However, no effort has been made to measure the behavior of electronics operating under the combined effects of both, EM noise and TID radiation. For the reasons pointed out, the combined-effect measurements should be mandatory when dealing with Systems-on-Chip (SoCs) devoted to critical applications. In this paper, we present a configurable platform devoted to perform combined tests of EM immunity and TID radiation of SoCs according to the international standards.

This paper presents a new hardware-based approach able to monitor the execution flow of the Real-Time Operating System (RTOS) in order to detect faults changing the tasks' execution flow in embedded systems. Results obtained during experiments performed according to the IEC 61000-4-29 standard demonstrate that the proposed approach is able to provide higher fault coverage with respect to the fault detection mechanisms natively provided by the RTOS.

The objective of this paper is to propose a performance failure prediction methodology for FPGA-based designs, based on the use of a novel built-in programmable delay sensor. Digital Clock Managers (DCM) is used to fine tune the unsafe observation interval. The design procedure is described, including the constrained placement of some delay sensors. The proposed technique is particularly useful to monitor parametric Process, supply Voltage and Temperature (PVT) and aging-induced variations. It can be used during product lifetime, as a predictive delay fault detection technique, either to avoid unreliable operation, or to guarantee correct functionality with lower power consumption. The usefulness of the proposed technique is demonstrated with part of the data processor of a complex design for a medical imaging system used in PET-based mammography, configured in a Virtex-4 FPGA device (xc4vfx60-11ff1152).

The use of Real-Time Operating Systems (RTOSs) became an attractive solution to simplify the design of safety-critical real-time embedded systems. Due to their stringent constraints such as battery-powered, high-speed and low-voltage operation, these systems are often subject to transient faults originated from a large spectrum of noisy sources, among them, the conducted and radiated Electromagnetic Interference (EMI). As the major consequence, the system's reliability degrades. In this paper, we present a hardware-based intellectual property (IP) core, namely RTOS-Guardian (RTOS-G) able to monitor the RTOS' execution in order to detect faults that corrupt the tasks' execution flow in embedded systems based on preemptive RTOS. Experimental results based on the Plasma microprocessor IP core running different test programs that exploit several RTOS resources have been developed. During test execution, the proposed system was exposed to conducted EMI according to the international standard IEC 61.000-4-29 for voltage dips, short interruptions and voltage transients on the power supply lines of electronic systems. The obtained results demonstrate that the proposed approach is able to provide higher fault coverage and reduced fault latency when compared to the native fault detection mechanisms embedded in the kernel of the RTOS.

This paper presents an efficient technique for designing high defect tolerance Static Random Access Memories (SRAMs) with significantly low power consumption. The new approach requires drastically lower area overhead, simpler encoding and decoding algorithms, and zero fault-detection latency time for multiple error detection when compared to conventional techniques. The approach is based on the use of Built-In-Current-Sensors (BICS) to detect the abnormal current dissipation in the memory power-bus to improve the reliability of H-Tree SRAM memories. This abnormal current is the result of a single-event upset (SEU) in the memory, and it is generated during the inversion of the state of the memory cell being upset (bit-flip). We demonstrate the assertions of the proposed approach with HSPICE simulations, and a reliability analysis that combines BICS with single-parity bit (or Hamming codes) per SRAM word to perform error correction. Furthermore, the basic infrastructure provided by this approach can also be used to dynamically reconfigure the SRAM memory to save power, and to leverage fabrication yield.

Wireless Sensor Networks (WSNs) can be used to monitor hazardous and inaccessible areas. The WSN is composed of several nodes each provided with its separated power supply, e.g. battery. Working in hardly accessible places it is preferable to assure the adoption of the minimum transmission power in order to prolong as much as possible the WSN’’s lifetime. Though, we have to keep in mind that the reliability of the data transmitted represents a crucial requirement. Therefore, power optimization and reliability have become the most important concerns when dealing with modern systems based on WSN. In this context, we propose to evaluate the effectiveness of a Transmission Power Self-Optimization (TPSO) technique for WSNs in an Electromagnetic Interference (EMI) Environment. The TPSO technique consists of an algorithm able to guarantee an equally high Quality of Service (QoS), concentrating on the WSN’’s Efficiency (Ef), while optimizing the transmission power necessary for data communication. Thus, the main idea behind our approach is to reach a trade-off between Ef and energy consumption in an environment with inherent noise.

Technology scaling has changed the Static Random Access Memory (SRAM) test scenario, leading to an insufficiency of the usually adopted functional fault models. In this sense, these fault models are no longer able to correctly reproduce the effects caused by some defects generated during the manufacturing process. In this paper, we investigate the possibility of using Built-In Current Sensors (BICSs) to detect static faults associated to resistive-open defects in SRAMs. Experimental results obtained throughout electrical simulations demonstrate the BICSs' capability to detect the considered faults, while resulting in negligible degradation on the SRAM access time.

Nowadays, Real-Time Operating Systems (RTOSs) are often adopted in order to simplify the design of safety-critical applications. However, real-time embedded systems are sensitive to transient faults that can affect the system causing scheduling dysfunctions and consequently changing the correct system behavior. In this context, we propose a new hardware-based approach able to detect faults that change the tasks' execution time and/or the tasks' execution flow in embedded systems based on RTOS. To demonstrate the effectiveness and benefits of using the proposed approach, we implemented a hardware prototype named Hardware-Scheduler (Hw-S) that provides real-time monitoring of the Plasma Microprocessor's RTOS in order to detect the above mentioned types of faults. The Hw-S has been evaluated in terms of the introduced area overhead and fault detection capability.

In nanometer technologies, as variability is becoming one of the leading causes for chip failures, signal integrity is a key issue for high-performance digital System-on-Chip (SoC) products. In this paper, analysis is focused on the occurrence of Delay-faults due to Power-supply disturbances in nanometer technologies. Using a previously proposed VT (power supply Voltage and Temperature)-aware time management methodology, it is shown that nanometer technologies impose the need of fault-tolerance methodologies, although the margins of tolerance or fault-free operations are being reduced as technology scales down. SPICE simulation results with 350 nm, 130 nm, 90 nm, 65 nm, 45 nm and 32 nm CMOS technologies show an increasing dependence of propagation delays on power supply variations, as technology is being scaled down. Monte Carlo simulations show that, even in the presence of process variations, a dynamic delay-fault tolerance methodology can be rewarding even at nanometer scale, although the margins for Power-supply variations are becoming smaller.

We propose an approach to optimize the number of checkpoints to be inserted along with an application code. The approach is based on a profiling process that analyzes the application code control-flow graph to find the best trade-off between the minimum number of checkpoints to be inserted in the code for a given fault detection coverage, with minimum impact in terms of power increase. The checkpoints are verified at runtime by the processor against compilation-time pre-computed values every time the processor reaches these points. Experiments with a PIC18 microcontroller have been carried out to demonstrate the benefits from using the proposed approach.

In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of the memory cell being upset. The current checking is performed on an H-tree SRAM in different ways. We demonstrate the assertions of the proposed technique by performing a reliability analysis while combining current monitoring with a single-parity bit or Hamming codes per RAM word to perform single or multiple error correction.

The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology is reviewed, highlighting its characteristics and limitations. The underlying principle is to introduce on-line additional tolerance, by dynamically controlling the time of the clock edge trigger driving specific memory cells. Second, it is shown that the proposed methodology is still useful in the presence of process variations. Third, discussion and preliminary results on the automatic selection (at gate level) of critical FF for which DDB insertion should take place are presented. Finally, it is shown that parametric delay tolerance insertion does not necessarily reduce delay fault detection, as multi-vdd or multi-frequency self-test can be used to recover detection capability.

In this paper, a new methodology is proposed to improve digital circuit signal integrity, in the presence of power-supply voltage (Vdd) and temperature (T) variations. The underlying principle of the proposed methodology is to introduce on-line additional tolerance, by dynamically controlling the instant of occurrence of the clock edge trigger driving specific memory cells. On-line, dynamic delay insertion in the clock signal driving such memory cells is performed, according to local VDDand/or T variations, using a dynamic delay buffer (DDB) block. The circuit becomes more tolerant to power line and temperature fluctuations, while maintaining at-speed clock rate. Moreover, when clock frequency reduction becomes unavoidable, the methodology improves signal integrity when the disturbances start to occur, allowing time for the clock generator to react and reduce its frequency. Experimental results based on SPICE simulations for two sequential circuits are used to demonstrate the usefulness of the proposed methodology.

This paper presents a new approach based on a watchdog infrastructure intellectual property (I-IP) core to detect control-flow faults that affect CPU execution time. More precisely, this approach aims at detecting those faults that change the expected CPU instruction sequence and that as consequence, change also (by increasing or reducing) the expected CPU time allocated for the execution of the monitored task. The underlined advantage of this approach is the ability of detecting faults in systems-on-chips (SoCs) simultaneously running multiple tasks under the control of a real-time (preemptive) operating system (OS). In this multi-task scenario, the I-IP performs fault detection in a time-shared basis. Practical experiments based on the IEC 62.132-2 Std. for IC electromagnetic immunity measurement have been carried out and the obtained results are discussed.

This paper summarizes a new approach based on a watchdog infrastructure intellectual property (I-IP) core to detect control-flow faults that affect CPU execution time. More precisely, this approach aims at detecting those faults that change the expected CPU instruction sequence and that as consequence, change also (by increasing or reducing) the expected CPU time allocated for the execution of the monitored task. The underlined advantage of this approach is the ability of detecting faults in multitask systems-on-chips (SoCs) running under the control of a real-time (preemptive) operating system. In this multi-task scenario, the I-IP can perform fault detection in a time-shared basis. Practical experiments have been carried out and results are discussed

Detection of physical defects (or transient faults) in nanometer products is very challenging. Parametric test, using variable power supply voltage, clock frequency and temperature can be rewarding. However, their impact on digital system performance needs to be evaluated. In this paper, a novel semi-empirical analytical model to compute, at logic level, the impact of power supply voltage variations (/spl Delta/V/sub DD/) and/or of temperature variations (/spl Delta/T) on speed response of a digital module is proposed. The model allows low-cost fault simulation. Moreover, it is shown that delay variation can be emulated either by a /spl Delta/V/sub DDi/ or a /spl Delta/Tj variation. The on-chip availability of multiple V/sub DD/ values in products with DVS (dynamic voltage scaling) opens opportunities for novel BIST techniques. A new DVS-based BIST approach is proposed and its ability to detect and diagnose resistive open defects is ascertained.

Hardening SoCs against transient faults requires new techniques able to combine high fault detection capabilities with the usual requirements of SoC design flow, e.g., reduced design-time, low area overhead, and reduced (or null) accessibility to source core descriptions. This paper proposes a new hybrid approach which combines hardening software transformations with the introduction of an Infrastructure IP with reduced memory and performance overheads. The proposed approach targets faults affecting the memory elements storing both the code and the data, independently of their location (inside or outside the processor). Extensive experimental results, including comparisons with previous approaches, are reported, which allow practically evaluating the characteristics of the method in terms of fault detection capabilities and area, memory, and performance overheads.

In sub-micron technology circuits high integration levels coupled with the increased sensitivity to soft errors even at ground level make the task of guaranteeing systems' dependability more difficult than ever. In this paper we present a new approach to detect control-flow errors by exploiting a low-cost infrastructure intellectual property (I-IP) core that works in cooperation with software-based techniques. The proposed approach is particularly suited when the system to be hardened is implemented as a system-on-chip (SoC), since the I-IP can be added easily and it is independent on the application. Experimental results are reported showing the effectiveness of the proposed approach.

Performance test is a powerful technique to identify difficult to detect defects. Recently, the authors have shown that multi-VDD test schemes may be used in a BIST environment to simulate multi-clock test. Using circuit and logic-level fault simulation it has been demonstrated that the effect of lowering VDD on the propagation delay time, while keeping invariant the observation pace at speed test, is similar to the effect of decreasing the clock period tCLKwhile keeping nominal VDD. In this paper, a simple analytical model to represent the dependence of propagation delay time variations of logic elements, Δpdon depleted VDD (i.e., on ΔVDD) is introduced. The model allows to back-annotate this dependence to logic-level fault simulation. As clock period decreases (or VDD decreases) failing vectors inducing errors are identified. Performance histograms, describing the dependence of the number of failing vectors on higher clock speed (or lower VDD) are used for delay fault detection and defect diagnosis. Basic infrastructures, ISCAS benchmarks and a combinational block of an industrial fleet management system, XTRAN, is used to demonstrate the results.

The following paper describes a new approach to perform physical fault injection in electronic systems. The approach is settled around a gigahertz transverse electromagnetic (GTEM) cell, which is employed in a controlled process to inject faults in the system under test (SUT). The assumed fault models are delay faults (provoked by signal propagation delay increase in SUT critical paths, thus resulting in de-synchronization between the computed data to be latched and the clock signal) and bit-flips (i.e., corruption of static data stored in memory elements).

Hereafter, we present an approach dealing to improve the reliability of digital signal processing (DSP) systems operating in real noisy (electromagnetic interference - EMI) environments. The approach is based on the coupling of two techniques: the "DSP-oriented signal integrity improvement" technique deals to increase the signal-to-noise ratio (SNR) and is essentially a modification of the classic Recovery Blocks Scheme. The second technique, named "SW-based fault handling" aims to detect in real-time data- and control-flow faults throughout modifications of the processor C-code. When compared to conventional approaches using Fast Fourier Transform (FIT) and Hamming Code, the primary benefit of such an approach is to improve system reliability by means of a considerably low complexity, reasonably low performance degradation and, when implemented in hardware, with reduced area overhead. Aiming to illustrate the proposed approach, we present a case study for a speech recognition system, which was partially implemented in a PC microcomputer and in a COTS microcontroller. This system was tested under a home-tailored EMI environment according to the International Standard Normative IEC 61.0004-29. The obtained results indicate that the proposed approach can effectively improve the reliability of DSP systems operating in real noise (EMI) environments.

In this paper, we present the last improvements for a new approach to cope with noise that troubles speech recognition systems (SRS). This approach performs on-line monitoring and is oriented to hardware redundancy (it is essentially a modification of the classic recovery block scheme). When compared to conventional approaches using fast Fourier transforms (FFT) and Hamming code, the primary benefit of such a technique is to improve system performance when operating in real (i.e., noisy) environments. The second advantage is related to the considerably lower complexity and reduced area overhead required for implementation. We implemented three full versions of the proposed algorithm: one running on a PC microcomputer, and a second one slightly modified to run on a TMS-320C67 Texas DSP microprocessor module. Both of them were described in the C language. A last implementation was prototyped on a hardware/software development environment based on the same Texas microprocessor and on the FLEX10K20 FPGA Altera component.

We present a new approach to design fault tolerant artificial neural networks (ANNs). Additionally, this approach allows estimating the final network reliability. This approach is based on the mutation analysis technique and is used during the training process of the ANN. The basic idea is to train the ANN in the presence of faults (single-fault model is assumed). To do so, a set of faults is injected into the code describing the ANN. This procedure yields mutation versions of the original ANN code, which in turn are used to train the network in an iterative process with the designer until the moment when the ANN is no longer sensible to the single faults injected. In other words, the network became tolerant to the considered set of faults. A practical example where an ANN is used to recognize an electrocardiogram (ECG) and to measure ECG parameters illustrates the proposed methodology.

This work proposes a speech recognition system based on a hardware/software co-design implementation approach. The main advantage in this approach is an expressive processing time reduction in speech recognition, because part of the system is implemented by dedicated hardware. This work also discuss another way to implement "hidden Markov models" (HMM), a probabilistic model extensively used in speech recognition systems. In this new approach, the Viterbi algorithm, used to compute the HMM likelihood score, will be "built in" together with the HMM structure designed in hardware, and implementing probabilistic state machines that will run as parallel processes one for each word in the vocabulary handled by the system. So far, we have a dramatic speed up performance, getting measures around 500 times faster than a classic implementation with the correctness comparable with others isolated word recognition systems.

We present a new approach to design reliable complex circuits with respect to transient faults in memory elements. These circuits are intended to be used in harmful environments like radiation. During the design flow this methodology is also used to perform an early-estimation of the obtained reliability level. Usually, this reliability estimation step is performed in the laboratory, by means of radiation facilities (particle accelerators). By doing so, the early-estimated reliability level is used to balance the design process into a trade-off between maximum area overhead due to the insertion of redundancy and the minimum reliability required for a given application. This approach is being automated through the development of a CAD tool (FT-PRO). Finally, we present also a case-study of a simple microprocessor used to analyze the FT-PRO performance in terms of the area overhead required to implement the fault-tolerant circuit.

This work presents an innovative approach for hardware/software codesign of safety-critical computing systems. The proposed approach is based on system reliability requirements to decide which parts of the system are partitioned into hardware or software. The approach considers as input a complete software description of the design. In our case, we use as the initial description the C language and then, for those parts compiled to hardware, the Handel-C language is applied. After partitioning, we verify system reliability based on an adaptation of the weak mutation analysis technique. This technique was originally proposed for software testing by means of verifying the adequacy of a test vector set for a given program. We also present a case study in order to illustrate the proposed approach.

This paper presents a new technique for designing reliable multichip modules (MCMs) under radiation effects for spacecraft electronics. The technique is based on current monitoring to detect faults induced by ionizing radiation in dies mounted on the MCM. These faults change transistor electrical parameters and increase power consumption due to increased leakage current. In addition to this fundamental benefit, the proposed approach can also be used to assess product quality during manufacturing testing.

Presents a novel approach to estimate the I/sub ddq/ current in faulty CMOS integrated circuits. This new methodology is not based on the prior knowledge of the faulty device resistance. Instead of that, the approach proposes the characterization of the quiescent current by evaluating the minimal power-bus current corresponding to an output voltage range characterized by the designer to be defective. This output voltage is defined by the designer in order to meet some desirable quality requirements for the circuit on the design, for instance, minimum acceptable noise immunity and maximum time delay. For the design of built-in current sensors, these quality requirements define the minimum current resolution. This approach is exemplified with the characterization of an in-house developed cell library.>