Electromagnetic fault injection (EMFI), which is a quite recent fault injection technique compared to laser fault injection, has gained in popularity these last years. Its increasing popularity can be probably explained by its inherent advantages among which the limited required preparation of devices can be viewed as the main one. The principle of EMFI consists in generating a powerful EM pulse in the close vicinity of ICs. To that aim a voltage pulse generator is used to induce a sudden current variation in probes, i.e. coils made of several wire turns around a ferrite core. However, EMFI is considered a fault injection technique with a poor spatial resolution mainly because EMFI probes are quite large. Increasing the spatial resolution of EMFI could be achieved by reducing the dimensions of probes. However, such a task is difficult and implies using more powerful voltage generators. Among the challenges to be addressed to enhance the spatial resolution of probes, one of the first ones is to determine how should be scaled the voltage pulse generators with the scaling of probe dimensions. This paper addresses this question from theoretical and practical points of view.

For monolithic heterogeneous integration, fast yet low-power processing and storage, and high integration density, the objective of the EU GREAT project is to co-integrate multiple digital and analog functions together within CMOS by adapting the Magnetic Tunneling Junctions (MTJs) into a single baseline technology enabling logic, memory, and analog functions, particularly for Internet of Things (IoT) platforms. This will lead to a unique STT-MTJ cell technology called Multifunctional Standardized Stack (MSS). This paper presents the progress in the project from the technology, compact modeling, process design kit, standard cells, as well as memory and system level design evaluation and exploration. The proposed technology and toolsets are giant leaps towards heterogeneous integrated technology and architectures for IoT.

"Beyond CMOS" is today one of the major research directions in semiconductor industries to address current integrated circuit issues. Many alternative technologies are currently under investigation to deal with the scaling limits of CMOS technology. This paper presents the design of a full system on chip based on a hybrid CMOS/Magnetic process. Spin-transfer-torque magnetic tunnel junctions are used to design different functions such as logic, memory, security and analog IP blocks.

This paper addresses a return of experience relative to the combination of several innovative educational approaches (classic lecture, per peers, and flipped classroom) to teach industrial test to undergraduate students from Polytech Montpellier engineering school. The objectives of the course were technical and educational: acquiring industrial test competencies in a way, students were the protagonists of their learning and for some topics they were the contributors of their peers'. At the end of the course, the teacher marked the students' skills and asked them to evaluate the course educational approaches completing a dedicated form created based on the F2A Louvain University one [1] to provide an objective and classifiable feedback. The paper presents the analysis of all results, states about this original experience and the future trends.

A novel resistive sensor interface for high temperature applications is presented. It is based on a time domain architecture using Injection Locked Oscillators as phase shifters that results in higher temperature hardness and simpler circuits. The system depends on the relative accuracy instead of its absolute properties and doesn't suffer from temperature variations. The proposed circuit is designed using 0.18 μm partially depleted silicon on insulator technology. Simulations have shown a maximum variation of the output lower than ±0.5%, over a temperature ranging from -40°C to 250°C.

This paper addresses a project-oriented pedagogy to teach industrial testing of integrated circuits (IC) to Polytech Montpellier 4th year engineering school students, using the test platform of the CNFM. The objectives of the course are double: technical and educational. The students have to acquire knowledge (IC test and diagnosis methods, test results and graph analysis technics) and competences relative to IC testing (test program development, debugging, graph interpretation, solving defects in a device). The students also have to be attentive to the course in order to identify their understanding and gaps, to understand the reasons of acquiring these competences and the required course steps to achieve this goal in order to become actor and author of their learning. The teaching sequence combines concepts presentations, a tutorial for students self-training on the tester software tool, a project to apply these concepts and use the tool and brainstorming phases using POSTIT to allow students stating about their learning.

Statistical analysis of analog circuits usually relies on the standard Monte Carlo method to estimate the yield of a circuit. However, this method is limited by a slow convergence rate which leads to a prohibitive number of simulations to reach a given accuracy. In this paper, we propose to combine the kernel-based distribution estimator with the control variates method in order to obtain an accurate yield estimation with only a few hundred simulations. With respect to the auxiliary variable needed for the control variates method, we propose a quick modeling technique based on local sensitivities.

In this paper, an alternative test method for MEMS convective accelerometers is presented. It is first demonstrated that device sensitivity can be determined without the use of physical test stimuli by simple electrical measurements. Using a previously developed behavioral model that allows efficient Monte-Carlo simulations, we have established a good correlation between electrical test parameters and device sensitivity. Proposed test method is finally evaluated for different strategies that privilege yield, fault coverage or test efficiency.

This paper presents an innovative conditioning and read-out interface for resistive MEMS sensors. The proposed structure includes a digital offset compensation for robustness to process and temperature variations. Simulation results demonstrate an impressive resolution to power consumption ratio and a good immunity to environmental parameters. Experimental results finally demonstrate the efficiency of this promising read-out architecture.

This paper presents a reconstruction technique based on zero-crossing detection that permits analyzing FM-modulated signals using digital ATE channels. The technique relies on sampling of the analog/RF signal through a 1-bit comparator and the post-processing of the resulting bit stream. The proposed solution is validated through both simulation and hardware experiments.

One of the main problems when developing analog filters in VLSI is to achieve high accuracy regarding the cutoff frequency. This is mainly due to the difficulty in obtaining accurate time constants. Testing of such filters is also challenging, in the sense that special equipment is required. Small deviations in the resistor or capacitor values may lead to a very high mismatch between the expected and the achieved cutoff frequency. Although switched-capacitor or active-transistor techniques may produce good results, the cost to use such approaches becomes another limiting factor, and only increases the tester needs. In this work, we present the development of an analog FIR filter, which does not use passive components to tune the cutoff frequency or the quality factor. Instead, the filter coefficients and the input signal are represented in a bit stream fashion, and are digitally processed, thus avoiding the use of expensive analog-to- digital converters. The impact of this filter architecture on test cost and possible design-for-test techniques are discussed in this paper.

This paper presents an electro-thermal on-line testing procedure applied to a MEMS magnetometer. The basic idea consists in: (i) using electro-thermal excitation to superimpose thermal variations to the normal operating mode; and (ii) processing the sensor output to extract the thermally-induced signal. In this work, we investigate the possibility of using a modulation of the excitation signal to produce a low-frequency thermally-based signal at the output of the Wheatstone bridge. Investigations using high-level simulations are conducted to determine appropriate test stimulus and suitable system architecture.

This paper introduces some practical BIST solutions as a basis for a future self-testable MEMS-based magnetic field sensor. It is demonstrated that slight modifications of the system architecture can be used to allow both on-chip generation of electro-thermal stimuli and preprocessing of the sensor response. The external response analysis and thus the test procedure are then strongly simplified and require only a standard digital automatic test equipment.

The development of low-cost go/no-go procedures for MEMS production testing is one of the main issues of MEMS manufacturability. In particular, the generation of low-cost test stimuli is a real challenge. In this paper, we investigate the generation of electrically-induced thermal stimuli to test electro-mechanical structures. Static, transient and harmonic responses are studied and it is demonstrated that they can be used for efficient detection and classification of several faulty devices.

This paper, which is mostly tutorial in nature, deals with the design of CMOS microelectromechanical systems MEMS using standard microelectronic computer-aided design tools. The proposed case study is an on-chip spectrum analyzer with an electronic mixer and a mechanical filter. Based on both analytical modeling and characterization, the filter is described using an analog hardware description language. System level simulations are then performed using a recently released simulation tool that offer new possibilities regarding the analysis of multidomain, multifrequency designs. Presented results include periodic steady state determination, small-signal analysis and noise investigation. The simulations demonstrate the ability of the proposed system to identify the harmonics of a 50-Hz square-wave signal, owing to the selectivity of the mechanical filter.

This paper introduces the use of the oscillation test technique for MEMS testing. This well-known test technique is here adapted to MEMS. Its efficiency is evaluated based on a case study: A CMOS electromechanical magnetometer.

In this paper, Oscillation-based Test Methodology (OTM) is evaluated in the context of MEMS testing. Both qualitative and quantitative evaluations of fault coverage are discussed and the impact of test on production yield is addressed. This article also introduces the Lorentz force as a low-cost stimulus for electro-mechanical structures.

This paper presents both the design and the characterization of a full CMOS magnetic field sensor. As an alternative to Hall effect sensors, it acts as a microscopic cantilever, deformed under the action of the Lorentz force.

This paper introduces a set of analytical formulations for 3D modelling of inter-layer capacitances. Efficiency and accuracy are both guaranteed by the process characterization approach. Analytical modelling of interconnect capacitances is then demonstrated to be an helpful alternative to lookup tables or numerical simulations.