CMOS scaling so far enabled simultaneous system throughput scaling by concurrent improvements in delay, power, and area with thanks to Moore's law. CMOS scaling becomes more difficult with the limits of interconnect and increasing wafer cost. It is empirical to consider the system-on-chip (SoC) context to choose the most critical process knobs since most of processing budget to scale a technology node is already consumed by increasing process steps due to multiple patterning. In this paper we will show that the device parasitics and the interconnect resistance are the most critical performance scaling barriers for technology nodes beyond 7 nm (N7). We will demonstrate the impact of process and design knobs enabling performance and power improvements for the N7 node as defined in ITRS 2015 edition while still continuing to scale the area to limit the cost.

CMOS scaling enabled simultaneous system throughput scaling by concurrent delay, power, and area shrinks with thanks to Moore's law. System scaling is getting more difficult with the limitations in interconnect and bandwidth per power as well as the difficulties and cost of monolithic integration. This requires a holistic approach for an optimal balance of performance and power under the limits of technology. This paper covers a portfolio of More Moore technologies for power-aware device enabling value proposition for system scaling - where requirements and gaps will be addressed in the ITRS2.0 roadmap.

This paper proposes TEASE (Technology Exploration and Analysis for SoC-level Evaluation), a framework to systematically analyze and evaluate system design in finFET-based technology node. The proposed framework combines both lithography and electrical constraints of a particular technology node to optimize the standard cell library performance. Growing complexity of logic design at nodes below 20nm causes to adopt a design style that can embrace the simplicity required to enable manufacturing, along with a process technology that can be finely tuned to the desired performance constraints. Additionally, the introduction of finFET based devices poses a new challenge for the designers to come up with an efficient standard cell template. The proposed framework can be used to detect the technology constraints that act as the bottleneck for the enablement of design at these advanced nodes. Results presented in this paper show by optimizing these bottlenecks we can improve the performance of a standard cell library significantly. Furthermore, adapting to such an analysis framework at an early stage of technology development helps to take the design constraints into the decision loop for realization of technology research into real products.

A digital integrated circuit (IC) is realized using the random neural network (RNN) model introduced by Gelenbe. The RNN IC employs both configurable routing and random signaling. In this paper we present the networking/routing aspects as well as the performance results of an RNN network implemented by the RNN IC. In the RNN model, each neuron accumulates arriving signals and can fire if its potential at a given instant of time is strictly positive. Firing occurs at random, the intervals between successive firing instants following an exponential distribution of constant rate. When a neuron fires, it routes the generated pulses to the output lines in accordance with the connection probabilities. The number of neurons in the network is programmable and could be connected to each other with any desired neuron interconnection and this connection could be changed on the fly. The RNN chip architecture is cascadable to generate any network topology. All the parts of the RNN circuit are implemented using a standard digital Complimentary-Metal-Oxide-Semiconductor (CMOS) process.

Due to high demand for hall sensors mostly in the automotive and industrial applications, development and manufacturing of hall sensors in System-on-Chip (SoC) became more important. On the other hand, options for test and characterization of hall sensors in manufacturing environment are very limited. In most cases external field generators are used in order to characterize the hall sensors on a small set of production samples. In this paper, we present our Coil- on-Chip (CoC) calibration methodology where there is no need for a dedicated setup/assembly. Our methodology is also immune to self-heating. Our methodology enables reduced costs in test equipment, 100% screening of hall sensors in manufacturing tests, and reliable trimming of sensitivity spread over temperature from -40degC to 150degC. Measurement results before trimming show less than 20% six-sigma spread for normalized sensitivity across 120 samples of different hall sensor structures processed in a 0.35 mum high-voltage CMOS process.

In this paper we present a macromodeling methodology to accurately reproduce the timing and the peak/average power behaviors of digital standard cells for a wide range of operating conditions determined by the load, the input transition time, and the supply variations. Our methodology significantly reduces the number of transient simulations for the cell characterization. The numerical results for the transient simulation of large digital systems indicate that we achieve a mean error of 10% for the power consumption and 4% for the propagation delay of the complete digital system while the mean error for the used gates in this system is 2.5% when compared to SPICE-based simulations.

Impulse-based ultra-wideband systems are appealing for low-power short-range communications as they can benefit from duty-cycled low-complexity analog architectures. Low-power receivers correlate in the analog domain and sample only at the pulse repetition frequency. However, achieving acquisition with such a receiver requires an efficient search strategy, as digital post-processing (equalization) of the signal is not possible. Moreover, as we target a network of ultra-low-power sensors which can only send a few pulses and do not implement receiver functionality in order to sustain ARQ protocols, the receiving base station has extra constraints on synchronization performance and maximal preamble length. This paper describes and optimizes a strategy compliant with that scenario, including pulse position and spreading code phase acquisition, end-of-preamble detection, and derivation of the corresponding detection thresholds. Based on a 300-bit preamble, it works within 1.5 dB of ideal synchronization on AWGN. EOP detection is analyzed, showing that a PN sequence of length 7 is sufficient, and also proposing optimal receive filters for EOP sequences defined in IEEE 802.15.4a. Finally, we show that on fading channels, the error floor coming from missed acquisitions can be removed by simply changing the detection threshold.

In a synchronous clock distribution network with negligible skews, digital circuits switch simultaneously on the clock edge; therefore, they generate a lot of substrate noise due to the resulting sharp peaks on the supply current. A solution is to split a large design in different clock regions and introduce intentional clock skews between them, while taking the timing constraints into account. In this paper, the authors present a complete design flow to optimize the clock tree for less substrate-noise generation in large digital systems. It proposes a technique to assign combinatorial cells and flip-flops to the clock regions. It also takes into account the impact of unintentional clock skew such as jitter on the computed skews in order to assure a robust design. During the optimization, it uses compressed supply-current profiles to improve the CPU time. Experimental results show more than a factor-of-2 reduction in substrate-noise generation from large digital circuits of which the skews are optimized

Substrate noise generated by the switching digital circuits degrades the performance of analog circuits embedded on the same substrate. It is therefore important to know the amount of noise at a certain point on the substrate. Existing transistor-level simulation approaches based on a substrate model extracted from layout information are not feasible for digital circuits of practical size. This paper presents a complete high-level methodology, which simulates a large digital standard cell-based design using a network of substrate macromodels, with one macromodel for each standard cell. Such macromodels can be constructed for both EPI-type and bulk-type substrates. Comparison of our substrate waveform analysis (SWAN) to several measurements and to several full SPICE simulations indicates that the substrate noise is simulated with our methodology within 10%-20% error in the time domain and within 2 dB relative error at the major resonance in the frequency domain. However, it is several orders of magnitude faster in CPU time than a full SPICE simulation.

In a synchronous clock-distribution network, digital circuits switch simultaneously on the clock edge; therefore, they generate ground bounce due to sharp peaks of the supply current. We demonstrate an effective combination of two methodologies for ground-bounce reduction based on shaping the supply current: 1) introducing intentional skews to the synchronous clock network and 2) frequency modulation of the system clock. The former technique reduces the time-domain peaks as well as the spectral power of the supply current by spreading the simultaneous switching activities. The latter technique reduces the power contained in the clock harmonics by spreading this power into the side lobes formed around the clock harmonics without any change in the spectral power of the supply current. We also describe an analytical framework to analyze the impact of cycle-to-cycle variations of the supply current on the ground-bounce voltage. Simulation results for a 40K-gates circuit in a 0.18-/spl mu/m 1.8-V CMOS process on a bulk-type substrate show around 26 dB reduction in the spectral peaks of the ground-bounce spectrum at the circuit resonance and factors of 3.04/spl times/ and 2.64/spl times/ reduction in the peak-to-peak and RMS values, respectively, of the ground bounce in the time domain when these two techniques are combined. These two techniques are believed to be good candidates for the development of digital low-noise designs in CMOS technologies.

Substrate noise is a major obstacle for mixed-signal integration. In this paper we propose a fast and accurate high-level methodology to simulate substrate noise generated by large digital circuits. The methodology can handle any substrate type, e.g. bulk-type or EPI-type, and takes into account the effects of interconnect and supply. For each standard cell a substrate macromodel is used in order to efficiently simulate the total system, which consists of a network of such macromodels. For a 40K gates telecom circuit fabricated in a 0.18 mm CMOS process, measurements indicate that substrate noise is simulated by using our methodology within 20% error but several orders of magnitude faster in CPU time than a full SPICE simulation..

The digital switching noise that propagates through the chip substrate to the analogue circuitry on the same chip is a major limitation for mixed-signal SoC integration. In synchronous digital systems, digital circuits switch simultaneously on the clock edge, hereby generating a large ground bounce. In order to reduce the spectral peaks in the ground bounce spectrum, we combine the two techniques: (1) phase modulation of the clock; and (2) introducing intended clock skews to spread the switching activities. Experimental results show around 16 dB reductions in the spectral peaks of the noise spectrum when these two techniques are combined. These two techniques are believed to be good candidates for the development of methodologies for digital low-noise design techniques in future CMOS technologies.

In a synchronous clock distribution network with zero latencies, digital circuits switch simultaneously on the clock edge, therefore they generate substrate noise due to the sharp peaks on the supply current. We present a novel methodology optimizing the clock tree for less substrate generation by using statistical single cycle supply current profiles computed for every clock region taking the timing constraints into account. Our methodology is novel as it uses an error-driven compressed data set during the optimization over a number of clock regions specified for a significant reduction in substrate noise. It also produces a quality analysis of the computed latencies as a function of the clock skew. The experimental results show >x2 reduction of substrate noise generation from the circuits having four clock regions of which the latencies are optimized.

Substrate noise generated by large digital circuits degrades the performance of analog circuits sharing the same substrate. Existing approaches usually extract the model of the substrate from the layout information and then simulate the extracted transistor-level netlist with this substrate model using a transistor-level simulator. For large digital circuits, the substrate simulation is however not feasible with a transistor-level simulator. In our previous work, it has been demonstrated that efficient and accurate simulation of substrate noise generation at gate-level is feasible. In this paper several important extensions to our previous work are introduced: modeling of I/O cells, modeling of input transition time and load dependency and the extraction methodology of an equivalent substrate model within multiple supply domains. Experimental results show an improved accuracy (6.3% error on RMS substrate voltage with respect to a full SPICE level simulation) with these extensions, while maintaining a large speedup with respect to SPICE simulations.

Substrate noise caused by large digital circuits will degrade the performance of analog circuits located on the same substrate. To simulate this performance degradation, the total amount of generated substrate noise must be known. Simulating substrate noise generated by large digital circuits is however not feasible with existing circuit simulators and detailed substrate models due to the long simulation times and high memory requirements. We have developed a methodology to simulate this substrate noise generation at a higher level. Not only does this methodology take noise coupling from switching gates into account, but also noise coupling from the power supply is included. This paper describes this simulation methodology. In the paper it is shown that the high-level simulations correspond very well with SPICE simulations and that a large gain in simulation speed is obtained. This high-level simulation methodology makes it possible to predict substrate noise generation of large digital circuits in a very efficient way, early in the design flow of mixed-signal ASICs.