EDBT 2026 Demo / reviewers in the wild / expert
Guhan Viswanathan
dblp:02/4993
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorSoftware engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Memory systems · 55% Parallel and multicore computing · 38% High-performance computing · 7% |
Topics — the 4 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache coherence |
0.0 | 1 | 1996 | Compiler-directed Shared-Memory Communication for Iterative Parallel Applications · SC 1996 |
Parallel and multicore computing › parallel computing › parallel communication
shared-memory communication |
0.0 | 1 | 1996 | Compiler-directed Shared-Memory Communication for Iterative Parallel Applications · SC 1996 |
Memory systems › memory architecture
memory system support |
0.0 | 1 | 1994 | LCM: Memory System Support for Parallel Language Implementation · ASPLOS 1994 |
Parallel and multicore computing › parallel computing › parallel programming languages
parallel language implementation |
0.0 | 1 | 1994 | LCM: Memory System Support for Parallel Language Implementation · ASPLOS 1994 |
Methods — techniques the papers use, named apart from their topics
runtime communication scheduling · 0.0dataflow analysis · 0.0compiler-controlled memory management · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | Compiler-directed Shared-Memory Communication for Iterative Parallel ApplicationsabstractMany scientific applications are iterative and specify repetitive communication patterns. This paper shows how a parallel-language compiler and custom cache-coherence protocols in a distributed shared memory system together can implement shared-memory communication efficiently for applications with unpredictable but repetitive communication patterns. The compiler uses data-flow analysis to identify program points where repetitive communication occurs. At runtime, the custom protocol builds communication schedules in one iteration and uses it to pre-send data in following iterations. This paper contains measurements on three iterative applications (including adaptive programs with unstructured data accesses) to show that custom protocols increase the number of shared-data requests satisfied locally, thus reducing the amount of time spent waiting for remote data. Guhan Viswanathan, James R. Larus |
SC | 1 |
| 1994 | LCM: Memory System Support for Parallel Language ImplementationabstractHigher-level parallel programming languages can be difficult to implement efficiently on parallel machines. This paper shows how a flexible, compiler-controlled memory system can help achieve good performance for language constructs that previously appeared too costly to be practical. James R. Larus, Brad Richards, Guhan Viswanathan |
ASPLOS | 3 |