Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Eiiti Wada

dblp:02/5279 · DBLP profile ↗
← Back
2ranked-venue papers
1as first author
0since 2021 · last 1996
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 83% Memory systems · 17%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design
0.011960
Esaki Diode High-Speed Logical Circuits · IRE Trans. Electron. Comput. 1960
Integrated circuit design › digital circuit design › logic design
logic circuits
0.011960
Esaki Diode High-Speed Logical Circuits · IRE Trans. Electron. Comput. 1960
Integrated circuit design › digital circuit design › logic families
tunnel diode logic circuits
0.011960
Esaki Diode High-Speed Logical Circuits · IRE Trans. Electron. Comput. 1960
Memory systems
delay-line memory
0.011960
Esaki Diode High-Speed Logical Circuits · IRE Trans. Electron. Comput. 1960
Memory systems › random-access memory
dynamic memory
0.011960
Esaki Diode High-Speed Logical Circuits · IRE Trans. Electron. Comput. 1960

Methods — techniques the papers use, named apart from their topics

subharmonic oscillator · 0.0majority logic · 0.0
YearPublicationVenuePosition
1996 Obituary: Professor Nobuo Yoneda (28 March 1930-22 April 1996)
Eiiti Wada, Akinori Yonezawa
Sci. Comput. Program.1
1960 Esaki Diode High-Speed Logical Circuits
abstract
Logical circuits using Esaki diodes, and which are based on a principle similar to parametron (subharmonic oscillator element) circuits, are described. Two diodes are used in series to form a basic element called a twin, and a binary digit is represented by the polarity of the potential induced at the middle point of the twin, which is controlled by the majority of input signals applied to the middle point. Unilateral transmission of information in circuits consisting of cascaded twins is achieved by dividing the twins into three groups and by energizing each group one after another in a cyclic manner. Experimental results with the clock frequency as high as 30 mc are reported. Also, a delay-line dynamic memory and a nondestructive memory in matrix form are discussed.
Eiichi Goto, Kenro Murata, Kisaburo Nakazawa, Keisuke Nakagawa, Tohru Moto-Oka, Yasushi Miatsu-Oka, Yoshihiro Ishibashi, Haruhisa Ishida, Takashi Soma, Eiiti Wada
IRE Trans. Electron. Comput.10