Classic AUTOSAR is a de facto standard for implementing automotive safety-critical systems. Building on its success, Adaptive AUTOSAR has been recently introduced to target applications that need both, a high performance, low real-time capability of an Adaptive platform, as well as a high real-time, low performance capability of a Classic one. The Adaptive part of these applications is mainly not required to conform to the highest ASIL C/D safety requirements where computations that depend on each other are always executed in the same order before a certain time point. Therefore, this paper proposes that deterministic execution is also relaxed for the Classic part of the applications.

One of the challenges encountered when processing streaming data is a change of the data distribution, which is called concept drift. It has been shown that ensemble methods are effective in reacting to such a change. However, so far it has not been investigated how the architecture and configuration of the ensemble, as well as the properties of the scenario, influence the prediction accuracy if the ensemble members (experts) are Long Short-Term Memory networks with an internal state. This paper evaluates six ensemble architectures in several configurations with regards to their suitability for processing streaming data with sudden, recurring concept drift. The evaluation with a public dataset shows the impact of the architecture and configuration on the ensembles’ accuracies, as well as the influence of the concepts’ stability periods and the Long Short-Term Memory experts’ internal states under several conditions.

One of the biggest advantages that a millimeter-wave (mmWave) system has is the tremendously available bandwidth. According to Shannon Theorem, an obvious improvement of the system capacity can be achieved. However, regarding an OFDM system, the number of subcarriers increases as well, although larger subcarrier spacing is considered in 5G. For the multiuser uplink transmission in an OFDM system, a baseband equalizer has to be computed on each subcarrier. Hence, an OFDM system with a great amount of subcarriers suffers from a high computation complexity while it benefits from the huge bandwidth. To reduce the system complexity, we introduce in this paper a simple subcarrier grouping scheme where only one equalizer is computed for a set of adjacent subcarriers. However, such scheme gives rise to a notable system degradation. Such a performance loss due to the subcarrier grouping can be further compensated by a time-domain linear filter.

The race towards autonomous driving provoked a paradigm shift as safety became a critical objective in the development of novel functionalities. The safety-critical part of these functionalities is predominantly realized in software complying to the AUTOSAR standard in which code fragments called runnables are configured at design-time to run according to a certain order and on a certain core. As a key technology that enables autonomous driving, machine learning is expected to play a significant role in automotive applications. Since machine learning algorithms inherently exhibit faults, e.g. a classifier's prediction is wrong with a relatively high rate, to enforce safety, fault tolerance techniques have to be used. Therefore, this paper proposes that this information is systematically used in the automatic configuration of an AUTOSAR system. Not to disrupt the usual software development process, the information is appended to already mapped and scheduled runnables. Then, a heuristic is presented to generate execution alternatives during design-time which are then selected at run-time to skip the intervals reserved for fault tolerance mechanisms in the prevailing case when no fault occurred. This novel idea considerably reduces execution time as demonstrated on real-world engine control software.

Automotive software has become immensely complex. To manage this complexity, a safety-critical application is commonly written respecting the AUTOSAR standard and deployed on a multi-core ECU. However, parallelization of an AUTOSAR task is hindered by data dependencies between runnables, the smallest code-fragments executed by the run-time system. Consequently, a substantial number of idle intervals is introduced. We propose to utilize such intervals in sporadic tasks by migrating runnables that were originally scheduled to execute in the scope of periodic tasks.

Efficient development of parallel software is one of the biggest hurdles to exploit the advantages of heterogeneous multi-core architectures. Fast and accurate compiler technology is required for determining the trade-off between multiple objectives, such as power and performance. To tackle this problem, the paper at hand proposes the novel heuristic TONPET. Furthermore, it is integrated into the SLX tool suite for a detailed evaluation and an applicability study. TOPNET is tested against representative benchmarks on three different platforms and compared to a state-of-the-art Evolutionary Multi Objective Algorithm (EMOA). On average, TONPET produces 6% better Pareto fronts, while being 18X faster in the worst case.

Deep neural networks usually possess a high overall resilience against errors in their intermediate computations. However, it has been shown that error resilience is generally not homogeneous within a neural network and some neurons might be very sensitive to faults. Even a single bit-flip fault in one of these critical neuron outputs can result in a large degradation of the final network output accuracy, which cannot be tolerated in some safety-critical applications. While critical neuron computations can be protected using error correction techniques, a resilience optimization of the neural network itself is more desirable, since it can reduce the required effort for error correction and fault protection in hardware. In this paper, we develop a novel resilience optimization method for deep neural networks, which builds upon a previously proposed resilience estimation technique. The optimization involves only few steps and can be applied to pre-trained networks. In our experiments, we significantly reduce the worst-case failure rates after a bit-flip fault for deep neural networks trained on the MNIST, CIFAR-10 and ILSVRC classification benchmarks.

Convolutional Neural Networks have become state of the art for many computer vision tasks. However, the size of Neural Networks prevents their application in resource constrained systems. In this work, we present a lossy compression technique for intermediate results of Convolutional Neural Networks. The proposed method offers guaranteed compression rates and additionally adapts to performance requirements. Our experiments with networks for classification and semantic segmentation show, that our method outperforms state-of-the-art compression techniques used in CNN accelerators.

To host intelligent algorithms such as Deep Neural Networks on embedded devices, it is beneficial to transform the data representation of neural networks into a fixed-point format with reduced bit-width. In this paper we present a novel quantization procedure for parameters and activations of pre-trained neural networks. For 8 bit linear quantization, our procedure achieves close to original network performance without retraining and consequently does not require labeled training data. Additionally, we evaluate our method for power-of-two quantization as well as for a two-hot quantization scheme, enabling shift-based inference. To underline the hardware benefits of a multiplierless accelerator, we propose the design of a shift-based processing element.

Hardware accelerators for compute intensive algorithms such as convolutional neural networks benefit from number representations with reduced precision. In this paper, we evaluate and extend a number representation based on power-of-two quantization enabling bit-shift-based processing of multiplications. We found that weights of a neural network can either be represented by a single 4 bit power-of-two value or with two 4 bit values depending on accuracy requirements. We evaluate the classification accuracy of VGG-16 and ResNet50 on the ImageNet dataset with weights represented in our novel number format. To include a more complex task, we additionally evaluate the format on two networks for semantic segmentation. In addition, we design a novel processing element based on bit-shifts which is configurable in terms of throughput (4 bit mode) and accuracy (8 bit mode). We evaluate this processing element in an FPGA implementation of a dedicated accelerator for neural networks incorporating a 32-by-64 processing array running at 250 MHz with 1 TOp/s peak throughput in 8 bit mode. The accelerator is capable of processing regular convolutional layers and dilated convolutions in combination with pooling and upsampling. For a semantic segmentation network with 108.5 GOp/frame, our FPGA implementation achieves a throughput of 7.0 FPS in the 8 bit accurate mode and upto 11.2 FPS in the 4 bit mode corresponding to 760.1 GOp/s and 1,218 GOp/s effective throughput, respectively. Finally, we compare the novel design to classical multiplier-based approaches in terms of FPGA utilization and power consumption. Our novel multiply-accumulate engines designed for the optimized number representation uses 9 % less logical elements while allowing double throughput compared to a classical implementation. Moreover, a measurement shows 25 % reduction of power consumption at same throughput. Therefore, our flexible design offers a solution to the trade-off between energy efficiency, accuracy, and high throughput.

The lack of technical resources and the high cost of establishing a semiconductor foundry has forced most integrated circuit design houses to rely on outsourcing part of their design and fabrication services to off-site companies. The involvement of external parties has given rise to major security threats, ranging from intellectual property piracy to the insertion of malicious circuits. Logic encryption has emerged as a popular mitigation technique against these threats. In recent years, a vast amount of logic encryption algorithms has been proposed. However, existing approaches strongly focus on isolated circuit components without taking the complexity and modular structure of modern circuit designs into account. In this paper, we propose Inter-Lock, a novel logic encryption framework tailored towards scaling logic encryption to larger designs by leveraging their complexity and exploiting multi-module interdependencies to exponentially enhance the security of sequential circuits. To showcase the applicability of the approach, we present an extensive evaluation on a real-life 32-bit RISC-V core together with the analysis of the security-cost trade-off. Our recommended Inter-Lock configuration of the core features a 1024-bit key and 100% functional corruption for 13.2% area overhead, less than 1% power overhead and 22.2% delay penalty in the worst case.

We present a Vector Processing Engine (VPE) designed for the acceleration of Convolutional Neural Networks (CNNs) for semantic segmentation. Most CNN accelerators focus on classification. However, CNNs for semantic segmentation incorporate special layer types. Our accelerator supports not only regular convolutional layers, but also dilated convolutions and convolutions in combination with down- or up-sampling. These features are implemented in dedicated address generators which load the corresponding input vector from an input line buffer. The VPE is designed as a 64x64-array where up to 64 output features and 64 input features of a convolutional layer can be unrolled in parallel. The array has a peak performance of 4.12 TOp/s and achieves 3.85 TOp/s on a CNN for semantic segmentation - resulting in an average utilization of 93 %. The design is prototypically implemented on a Virtex UltraScale+ device with a clock rate of 250 MHz. In addition to the overall architecture, we present the two-hot quantization scheme. A value in two-hot quantization can be regarded as a combination of two power-of-two values. Hence, instead of bulky multipliers, two small bit-shifts are implemented. We design and implement dedicated arithmetic engines for this quantization scheme. Additionally, we evaluate this quantization scheme on the rather complex task of semantic segmentation. We show that the performance of an 8 bit two-hot quantization scheme is marginally lower in comparison to a regular 8 bit fixed-point variant.

Malicious circuit modifications known as hardware Trojans represent a rising threat to the integrated circuit supply chain. As many Trojans are activated based on a specific sequence of circuit states, we have recognized the ease of utilizing an instruction sequence for Trojan activation inside a processor core as a significant security issue. To protect against this threat, we propose Control-Lock: a novel methodology for securing inter-module control signals against software-controlled hardware Trojans, even if the signals are known to the adversary during fabrication. We demonstrate the approach with a RISC-V processor infected with a denial of service Trojan. We evaluate different Control-Lock encryption schemes with regards to the security-cost trade-off. Our results show that protecting a processor against a software-controlled hardware Trojan exploiting code execution implies an area overhead of only 4.75% as well as a negligible delay and power overhead.

This paper adapts and extends the previously published hierarchical modelling approach of multifunction radars as systems that speak a language. We propose Long Short-Term Memory neural networks for learning the emitters' grammar and predicting their emissions. The approach is demonstrated using simulations of an airborne multifunction radar with three different resource management techniques of varying complexity. A comparison with simple prediction strategies shows that a huge improvement in accuracy can be achieved by using Long Short-Term Memory networks for predicting complex radar emitter behaviour.

In recent years, neural networks have surpassed classical algorithms in areas such as object recognition, e.g. in the well-known ImageNet challenge. As a result, great effort is being put into developing fast and efficient accelerators, especially for Convolutional Neural Networks (CNNs). In this work we present ConvAix, a fully C-programmable processor, which - contrary to many existing architectures - does not rely on a hard-wired array of multiply-and-accumulate (MAC) units. Instead it maps computations onto independent vector lanes making use of a carefully designed vector instruction set. The presented processor is targeted towards latency-sensitive applications and is capable of executing up to 192 MAC operations per cycle. ConvAix operates at a target clock frequency of 400 MHz in 28nm CMOS, thereby offering state-of-the-art performance with proper flexibility within its target domain. Simulation results for several 2D convolutional layers from well known CNNs (AlexNet, VGG-16) show an average ALU utilization of 72.5% using vector instructions with 16 bit fixed-point arithmetic. Compared to other well-known designs which are less flexible, ConvAix offers competitive energy efficiency of up to 497 GOP/s/W while even surpassing them in terms of area efficiency and processing speed.

Autonomous wireless agents are deployed in difficult to approach environments in order to gather information for example temperature, pressure or pollution distributions. Although the size and cost of agents decrease, their batteries are generally insufficient for the desired measurement duration. In this study, adaptive sampling techniques are considered to prolong the agents operation time. This is achieved via adaptations of the agents' sampling periods while minimizing the information loss. Accordingly, exponential double smoothing adaptive sampling (EDSAS) is operated and Wiener filter based adaptive sampling (WFAS) is proposed considering the limited energy capacity of the agents. This study demonstrates the performance of deterministic and stochastic adaptive sampling strategies for real data in terms of reconstruction error, achieved data reduction rate and minimum sampling rate. Simulation results show that agents are able to decrease their sampling rate up to 10 which is equivalent to achieve a data reduction around 80 percent. In addition, it is also demonstrated that the proposed WFAS algorithm is superior to the EDSAS algorithm in terms of improved data reduction rate, and correspondingly, energy efficiency through relaxed error tolerances while maintaining a reasonable reconstruction performance.

Cyber-physical systems (CPS) are state-of-the-art communication environments that offer various applications with distinct requirements. However, security in CPS is a nonnegotiable concept, since without a proper security mechanism the applications of CPS may risk human lives, the privacy of individuals, and system operations. In this paper, we focus on PHY-layer security approaches in CPS to prevent passive eavesdropping attacks, and we propose an integration of physical layer operations to enhance security. Thanks to the McEliece cryptosystem, error injection is firstly applied to information bits, which are encoded with the forward error correction (FEC) schemes. Golay and Hamming codes are selected as FEC schemes to satisfy power and computational efficiency. Then obtained codewords are transmitted across reliable intermediate relays to the legitimate receiver. As a performance metric, the decoding frame error rate of the eavesdropper is analytically obtained for the fragmentary existence of significant noise between relays and Eve. The simulation results validate the analytical calculations, and the obtained results show that the number of low-quality channels and the selected FEC scheme affects the performance of the proposed model.

Modern process automation and the industrial evolution heading towards Industry 4.0 require a huge variety of information to be fused in a Cyber-Physical System. Important for many applications is the spatial position of an arbitrary object given directly or indirectly in terms of data that has to be processed to obtain position information. Starting point for the idea of the technical reflection-based sound localization system presented in this paper is the biological role model of humans being able to learn how to localize sound sources. Compared to other forms of sound localization, this nature-inspired method has no need for high spatial and temporal accuracy or big microphone arrays. Possible applications for this system are indoor robot localization or object tracking.

Virtual platform (VP) technology is an established enabler of embedded system design. However, the sheer number of CPU models in modern multi-core VPs forms a performance bottleneck. Hybrid simulation addresses this issue by executing parts of the embedded software stack on the host. Although the approach is significantly faster, hybridization can not cope with higher software layers, e.g., Operating Systems (OSs). Thus, this paper presents the OS-aware Host EXtension (OHEX) framework to accelerate VPs while expanding the applicability of hybridization. OHEX is evaluated on various system layers, yielding speedups between 2.99x-21.14x with specific benchmarks.

Deep neural networks have become a ubiquitous tool for mastering complex classification tasks. Current research focuses on the development of power-efficient and fast neural network hardware accelerators for mobile and embedded devices. However, when used in safety-critical applications, for example autonomously operating vehicles, the reliability of such accelerators becomes a further optimization criterion which can stand in contrast to power-efficiency and latency. Furthermore, ensuring hardware reliability becomes increasingly challenging for shrinking structure widths and rising power densities in the nanometer semiconductor technology era. One solution to this challenge is the exploitation of fault tolerant parts in deep neural networks. In this paper we propose a new method for predicting the error resilience of neurons in deep neural networks and show that this method significantly improves upon existing methods in terms of accuracy as well as interpretability. We evaluate prediction accuracy by simulating hardware faults in networks trained on the CIFAR-10 and ILSVRC image classification benchmarks and protecting neurons according to the resilience estimations. In addition, we demonstrate how our resilience prediction can be used for a flexible trade-off between reliability and efficiency in neural network hardware accelerators.

Efficient acceleration of Deep Neural Networks is a manifold task. In order to save memory requirements and reduce energy consumption we propose the use of dedicated accelerators with novel arithmetic processing elements which use bit shifts instead of multipliers. While a regular power-of-2 quantization scheme allows for multiplierless computation of multiply-accumulate-operations, it suffers from high accuracy losses in neural networks. Therefore, we evaluate the use of powers-of-arbitrary-log-bases and confirmed their suitability for quantization of pre-trained neural networks. The presented method works without retraining of the neural network and therefore is suitable for applications in which no labeled training data is available. In order to verify our proposed method, we implement the log-based processing elements into a neural network accelerator on an FPGA. The hardware efficiency is evaluated in terms of FPGA utilization and energy requirements in comparison to regular 8-bit-fixed-point multiplier based acceleration. Using this approach hardware resources are minimized and power consumption is reduced by 22.3%.

While half and full duplex wireless enabled cyber physical systems (CPSs) are gaining more importance and research attention, maintaining the security of CPS systems remains a vital challenge. The broadcast nature of wireless channels makes it possible for unauthorized receivers, called eavesdroppers, to capture the information signal. Wireless physical layer security techniques aim to harden the secrecy characteristics of wireless systems, decreasing the signal quality of a prospective eavesdropper. This paper considers a joint optimization of artificial noise (AN) signal and transmit filter for the information signals in order to achieve a target secrecy level. As eavesdropping attacks are very critical threats in CPS networks, and the need for high secrecy techniques remains valid. The proposed framework includes a scenario with two multi-antenna legitimate parties and a multi-antenna eavesdropper node (or multiple cooperating eavesdroppers). The transmit filter and AN signal are jointly optimized by the transmitters, where receiver nodes can make use of optimal transmit filters. The problem is derived for the cases where the legitimate CPS nodes perform full duplex and half duplex transmissions. The impact of channel estimation errors and self interference are also discussed.

Parallelizing compilers are a promising solution to tackle key challenges of MPSoC programming. One fundamental aspect for a profitable parallelization is to estimate the performance of the applications on the target platforms. There is a wide range of state-of-the-art performance estimation techniques, such as, simulation-based, measurement-based, among others. They provide performance estimates typically only at function or basic block granularity. However, MPSoC compilers require performance information at other granularities, such as statement, loop or even arbitrary code blocks. In this paper, we propose a framework to adapt performance information sources to any granularity required by an MPSoC compiler.

MPSoC programming is still a challenging task, where several aspects have to be taken into account to achieve a profitable parallel execution. Selecting a proper scheduling policy is an aspect that has a major impact on the performance. OpenMP is an example of a programming paradigm that allows to specify the scheduling policy on a per loop basis. However, choosing the best scheduling policy and the corresponding parameters is not a trivial task. In fact, there is already a large amount of software parallelized with OpenMP, where the scheduling policy is not explicitly specified. Then, the scheduling decision is left to the default runtime, which in most of the cases does not yield the best performance. In this paper, we present a schedule-aware optimization approach enabled by exploiting the parallel slack existing in loops parallelized with OpenMP. Results on an embedded multicore device, show that the performance achieved by OpenMP loops optimized with our approach outperform by up to 93%, the performance achieved by the original OpenMP loops, where the scheduling policy is not specified.

In this paper, massive MIMO amplify-and-forward multi-pair relaying is considered to assist device-to-device (D2D) communications. The direct D2D communication is underlaid with the source-to-relay transmission in the first hop, hence the D2D signals are also received at the relay, which are then forwarded in the second hop, overlapping with the relay-to-destination transmission. Moreover, D2D users are assumed to be able to harvest energy from the relay signal. Therefore, the D2D receivers, who failed in the direct D2D, can perform information detection (ID) with an opportunistic energy harvesting (EH) in the second hop. Closed-form deterministic equivalents of the associated signal to interference-plus-noise ratio in the ID and the harvested energy in the EH are derived, for both the maximum ratio combining/transmission and zero-forcing based relaying. A particular result of the asymptotic analysis indicates that the transmit power of source users can be made inversely proportional to the number of relay antennas, such that non-vanishing relay assisted D2D rate and harvested energy of D2D users exist. Simulations validate the analytical results, and illustrate the capability of massive MIMO relaying in assisting D2D via the so-called rate-energy region.

In a practical large scale antenna system (LSAS) over the millimeter Wave (mmWave) bands, the implementation of hybrid beamforming structure plays an important role as it provides high precoding gains to overcome the high path loss and achieve sufficient link margins. While employing such large antenna arrays, it becomes challenging to estimate the mmWave channel using the conventional algorithms. In this paper, we develop two novel multi-resolution mmWave channel estimation algorithms that exploit two dimensional discrete Fourier transform technique inspired by the sparse nature of the mmWave channel. The proposed algorithms take into account practical radio frequency (RF) hardware limitations and computational complexity reduction during the training phases. Numerical results indicate that the proposed algorithms can achieve a comparable spectral efficiency with respect to the case when perfect channel state information is known.

Machine Learning techniques such as Support Vector Machines (SVM) have found applications in many fields, e.g. in Wireless Sensor Networks (WSN) and sensor data processing in general. Especially in the case of WSN energy is very limited as agents solely operate based on battery power after they have been deployed, therefore energy efficiency is of great importance. Furthermore, agents are supposed to adapt to their environment by being capable of re-training themselves based on feedback they get from their surroundings, which increases the computational demands on the digital hardware involved. To meet these demands, dedicated hardware in form of a very-large-scale integrated (VLSI) circuit is a reasonable approach and is investigated here. In this paper a specific variant of the SVM — the Least-Squares SVM — is implemented as VLSI circuit. Additionally during the training phase a subset-selection technique based on the quadratic Renyi entropy is implemented in order to reduce the computational and hardware demands. The resulting design consumes 21.35 mW and requires an area of 81.2 kGE without memories.

As private information of individuals become more accessible, data privacy evolved to be an important aspect of communication technologies. Among existing privacy definitions, the utility privacy trade-off model is suitable for the assessment of privacy due to its relation with the information theory and the rate distortion theory. In this paper, the effects of the transmission errors due to the wireless channel are studied with respect to the utility privacy trade-off in a wireless communication network. First, the transmission error probability is embedded to the existing trade-off definitions. Then, it is shown via numerical examples that binary and normal distributed sources comply with the limits that are set by the updated rate distortion equivocation and equivocation distortion functions.

In this paper the millimeter wave (mmWave) single carrier transmission systems operating on wideband channels with frequency selectivity are considered. We propose two frequency selective hybrid precoding solutions, namely time delay compensation (TDC) based time domain equalization (TDE) and phase shift compensation (PSC) based frequency domain equalization (FDE). First, we implement a sectorized beamforming in RF domain to compensate the large path-loss at mmWave range and reduce the intra cluster delay spread. Here, the RF precoder is assumed to be frequency flat during one block transmission due to the independence of RF precoder design on the time delay spread. Subsequently, adopting TDC for TDE and PSC for FDE in digital baseband to reduce frequency selectivity, the baseband precoder is designed to maximize the achievable capacity. Finally, numerical results indicate that the proposed equalization algorithms can achieve a comparable performance with respect to the flat channel case.

The privacy risks for individuals are becoming more concrete in communication systems, and existing privacy protection methods may not be suitable in communication systems. Among existing privacy definitions, the utility privacy trade-off is proper evaluation model of privacy in communication systems due to its relation with information theory and rate distortion theory. In this paper, at first we theoretically investigate the utility privacy trade-off on noisy channels and derive the updated expressions for trade-off functions. Then, these functions are both simulated and tested with software defined radios (SDRs) for orthogonal frequency division multiplexing (OFDM) based wireless communication system.

The fast-evolving standards of the wireless communication systems drive the demand for flexible baseband processing platforms. However, with the proliferation of MIMO technologies, traditional single-core-based solutions are hardly able to fulfill requirements with acceptable power and area cost. The reliance on multi-/many-core system is increasing. Different from the computation-limited single-core-based solutions, multi/many-core systems are often communication-limited. In this paper, aiming at MIMO interference cancellation algorithms, we propose a flexible master-slave-based multiprocessor system-on-chiparchitecture based on a systematically divide-and-conquer approach to optimize the communication problems from the application-, architecture- and programming-levels. First, a comprehensively analysis of several typical applications in terms of parallelism, communication patterns and computation patterns is presented. According to the analysis results, a low-complexity and flexible ad hoc point-to-point interconnected fine-grained programmable-element (f -PE) is proposed to execute the arithmetic calculation. In order to reduce the communication traffic, an f-PE-based slave-node is constructed to exploit the data and instruction localities of applications, and a master node that is used to schedule and serve data for the slave nodes is also integrated. Furthermore, to improve the ease of use of the architecture, a multiple instruction multiple data like programming model is adopted and an optimizing mapping strategy is developed. In order to show its flexibility potential, seven linear and nonlinear IC algorithms with distinct computation natures are implemented on the proposed architecture. Finally, the gate-level synthesis and postlayout results are presented to demonstrate the strength and weaknesses of our design.

MPSoCs have evolved into heterogeneous architectures, where general purpose processors are combined with accelerators. Directive-based programming models such as the OpenMP 4.0 accelerator model have emerged as an approach to parallelize and offload code regions to accelerators. However, existing compiler technologies have focused mainly on parallelization, leaving the challenging task of offloading code regions to the developers. In this paper, we propose a novel approach that addresses parallelization and offloading jointly. Results show that our approach is able to speedup sequential embedded applications significantly on a commercial heterogeneous MPSoC, which incorporates a quad-core ARM cluster and an octa-core DSP cluster.

The physical layer security in a multi-user massive multiple-input multiple-output (MU-Massive-MIMO) system is considered in this paper, where a hidden eavesdropper (Eve) may eavesdrop the information signal of any legitimate user. Two distributed antenna system (DAS) aided power-saving transmit strategies are evaluated: 1) the autonomous full (AF) transmission with explicit artificial noise (AN), and 2) the autonomous DAS (AD) scheme, in which the AN is implicitly generated. Based on the cooperative maximum-ratio transmission and derived closed-form deterministic equivalents of the signal to interference-plus-noise ratios (SINRs) of users and Eve, we minimize the sum transmit power subject to the security constraints on the SINRs. The optimizations in both schemes are complementary geometric programming. In particular, the AD scheme depends on the signal to AN power ratio, which is controlled either by an unified or autonomous multiplicative parameter. In simulations, we illustrate that the sum power consumed in the AD scheme with autonomous parameter is less than the unified case as well as the AF scheme, hence it improves the power-saving in MU-Massive-MIMO with security guarantee.

We consider in this paper the physical layer security of multi-pair communication in massive MIMO aided amplify-and-forward (AF) relaying, where an eavesdropper (Eve) may intercept the information intended to any of the destinations. We derive closed-form deterministic equivalents of the end-to-end signal to interference-plus-noise ratios of legitimate users and Eve. We assume that the AF processing as well as the artificial noise generated at the relay are based on the imperfect channel state information of both hops. A particular result of the asymptotic analysis shows that by simply increasing the transmit power at the sources or relay the reachable security is limited by an upper bound. Nevertheless, the security can be strongly improved with a low-complexity power control at the relay, whose performance is evaluated in simulations.

Downlink (DL) transmission performance highly relies on the accuracy and delay of the quantized channel state information (CSI) feedback, which is conversely an overhead for the system. Therefore, net throughput is an advisable criteria to design the feedback scheme. Unlike previous works, we firstly provide a quantized channel prediction method by calculating the error variance of random vector quantization (RVQ) to reduce the performance degradation due to channel varying during two successive feedback intervals. With the derived probability distribution function (p.d.f.) of the predicted signal-to-noise ratio (SNR), the DL data rate is then described by considering packet error rate (PER) caused by overestimated SNR. Finally the net throughput is maximized by optimizing the number of feedback bits and time interval. Link-level simulation results show that the feedback scheme depends on user mobility and channel condition (SNR). For multiuser scenario, the feedback schemes are optimized for user groups based on mobility and DL SNRs in order to reduce complexity.

Large scale antenna systems (LSAS) in the mmWave bands provide a solution to the problems of spectrum shortage experienced in the conventional microwave bands. In a practical large scale antenna deployment, implementation of hybrid beamforming structures is very important as it provides high array gains to overcome the high path loss and achieve sufficient link margins. However, while implementing this we encounter the challenges such as complexity, cost and energy consumption. In this paper a power consumption model for the large scale antenna mmWave system is presented and analysed. From the power consumption model we maximize the energy efficiency of the overall system. Optimization of energy efficiency is a crucial factor in system optimization and design of the powerhungry devices. But with increasing energy efficiency, the spectral efficiency decreases. Thus analysis of the relation between energy and spectral efficiency becomes a critical task and we optimize energy efficiency at a fixed spectral efficiency. The results can then be utilized to guide the practical energy/spectrum efficiency trade-off for the LSAS design.

The fading channel in mmWave communications has a very high chance to be frequency selective owing to the large transmission bandwidth. To overcome the frequency selectivity we propose a novel method, namely RF beamforming with time delay compensation. Simultaneously, baseband precoder at the transmitter side and the combiner at the receiver side are employed to maximize the capacity of the system. For effectively flattening the channel by beamforming on both sides, it is necessary to separate the individual rays. Motivated by achieving the best case beam separation, a signal-to-interference ratio (SIR) constrained capacity maximization algorithm is proposed in this paper. We also study the influence of the parameters such as the number of antennas at the transmitter side and the SIR threshold on the capacity and the system performance. Finally, the proposed method is validated by providing numerical examples by means of simulation.

We consider a time-division duplexing multi-user massive multiple-input multiple-output system, where a so-called beamforming training (BFT) occurs prior to the downlink (DL) data transmission. The BFT process helps the users to obtain the estimates of effective channels, and thus facilitates a more reliable DL data detection compared to the conventional case, where the users have only the statistic channel knowledge. We first derive the closed-form lower bounds on the achievable DL data rates in the conventional and BFT schemes, using the minimum mean-square-error (MMSE) precoder. This enables us to further analyze the spectral efficiency, which takes the loss due to the training overhead into account. Moreover, we also consider a realistic scenario where the channel aging is present: it may destroy the training gain and lead to an efficiency loss. The effects of channel aging in both schemes are evaluated. In simulations, the performance of MMSE precoder is compared to the maximum-ratio transmission and zero-forcing precoding methods for both schemes in the static and aging channels.

The flexibility and programmability of an application-specific instruction-set processor (ASIP) come at the expense of reduced area and energy efficiency compared to application-specific integrated circuit (ASIC) solutions. Nevertheless, ASIPs are desirable for versatile application domains like wireless communications and software defined radio (SDR). Typically, ASIP designers reduce the ASIC-ASIP efficiency gap by increasingly complex architectures with decreasing flexibility and usability. This paper takes the opposite approach and presents concepts for a highly efficient, lightweight SDR ASIP. Efficiency enablers include simple but effective measures like a carefully chosen instruction set, optimized data access techniques for efficient utilization of functional units, and the use of flexible floating-point arithmetic with runtime-adaptive numerical precision. We present a conceptual processor core to show the impact of these measures and discuss its potential as well as limitations compared to tailored ASIC solutions. For demonstration, we choose the field of linear multiple-input multiple-output (MIMO) detection. We present synthesis results for several design versions in 90 nm CMOS technology and the corresponding energy benchmarks. Also, we show post-layout results for a selected design to demonstrate the feasibility of our concept.

We consider the physical layer security in a multi-user massive multiple-input multiple-output system, where an eavesdropper (Eve) can intercept the information intended for any of the legitimate users. Several remote radio heads (RRHs), each equipped with massive antennas, are deployed to create the distributed antenna system (DAS). With the cooperative maximum-ratio transmission, we propose three secure transmit strategies, i.e., the centralized and autonomous full (CF & AF) transmissions with explicit artificial noise (AN), and the autonomous DAS (AD) scheme using implicit AN. We first derive closed-form deterministic equivalents of the signal to interference-plus-noise ratios (SINRs) of users and Eve for all the schemes. Then, we formulate two security-constrained power allocation problems aiming at: 1) maximizing the minimum user SINR and 2) minimizing the sum transmit power. Except for the optimization in the CF scheme, which yields linear programming, all others result in complementary geometric programming (GP), and are solved by successive approximations into ordinary GP. Numerical results demonstrate: 1) the significance of deploying the RRHs and autonomous power allocation to increase the user SINR; 2) the notable power-saving in the AF scheme; and 3) the improved power reduction in the AD scheme with a limited number of RRHs and antennas per RRH.

Modern multi- and many-core systems are prone to concurrency-related bugs that surface only at system level. Detecting these bugs might require dealing with low-level hardware (HW) protocols and/or software (SW) inter-task interactions. Virtual platforms (VPs) offer a vehicle to conveniently debug HW/SW functionality, yet developers are mostly limited to manually breakpoint, step and interact with the system. To ease debugging during integration at system level, this paper introduces SWAT, an assertion-based debugging framework that checks and correlates system-wide interactions among HW and SW components. SWAT is used together with VPs to enable detecting HW/SW concurrency bugs with lower effort than traditional manual techniques. Our proposed approach is evaluated on two state-of-the-art platforms running real-world SW stacks.

Modern cars require powerful multi- and manycore hardware platforms to fulfill the demands of upcoming computationally intensive advanced driver assistance systems. This leads to a distributed hardware/software architecture that poses an unbearable system complexity to designers. Additionally, the strict requirements of new functional safety standards make it extremely difficult to rapidly and comprehensively close the development-evaluation-debug cycle. To overcome these complications, virtual platform technology is a promising approach that provides full hardware/software visibility, controllability and adequate simulation speed at electronic system level. However, for highly heterogeneous systems, such as modern cars, this technology lacks the capability to capture and integrate interactions of multiple subsystems beyond the hardware/software domain. To bridge this gap, this work presents multiple methods to facilitate the integration of virtual platforms into complex heterogeneous multi-domain vehicular simulation systems via the Functional Mock-Up Interface (FMI), the de facto co-simulation standard for automotive. The presented approaches significantly increase the depth of functional safety testing, as holistic car simulation covers cross-domain interactions of its subsystems.

We propose an efficient iterative multiple-input multiple-output (MIMO) detection algorithm based on the local search. Specifically, since the MIMO channel matrix twists the lattice structure of the received symbols, the proposed channel-aware local search (CA-LS) defines its search neighborhood according to the instantaneous channel realization. Such channel-dependent neighborhood can be efficiently identified by using the sphere decoder in a set that comprises the differences between pairs of QAM vectors, which is termed as delta vectors. The delta vectors with small quadratic norms with respect to the channel matrix are identified and then used as the search directions of the CA-LS. Features like sparsity and non-uniformity of delta vectors are exploited to reduce the SD complexity. Furthermore, by reformulating the detection criterion, the log-likelihood ratio (LLR) computations and searches of the CA-LS are greatly simplified. Numerical simulations demonstrate that compared with other practical iterative MIMO detectors, e.g., the list sphere decoder, the CA-LS achieves superior performance in both error rate and complexity aspects.

Enhanced Inter Cell Interference Coordination (eICIC) is a time-domain technique to achieve load balancing among macro and pico cells in heterogeneous networks (HetNets). eICIC uses two network parameters to address the interference problem: i) Cell Range Extension (CRE) to increase the coverage of pico cells; ii) Almost Blank Subframe (ABS) to reduce the interference for users in pico cells when macro cells keep mute. The majority of previous work only considered network parameter optimization for users with fixed locations. In this paper, we jointly optimize CRE bias and ABS ratio for users with mobility based on near-future channel conditions within a long-term near-future time window. With this purpose we introduce a signal-to-interference-plus-noise ratio (SINR) map, which is a geographical map with overlay average SINR values upon map pixels. Combined with mobility prediction, the near-future channel conditions within the scheduling window can be predicted. Simulation results illustrate the performance gain brought by the proposed algorithm.

Due to the very large transmission bandwidth of millimeter wave (mmWave) communications, the fading channel is expected to be frequency selective. Recent work in this field has mainly focused on cyclic-prefixed OFDM as a method to combat the frequency selectivity. But in this paper, we shift the focus on the novel method of time delay compensation to obtain a flat channel over wide bandwidth since it proves to be a more effective method reducing the computational complexity and achieving the high power efficiency at the receiver side. We employ time-shifted beams to compensate the delay spread and achieve high directionality. We also study the influence of physical parameters such as delay spread and system parameters such as the number of antennas on ergodic capacity and outage capacity. Finally, the proposed method is validated by providing numerical examples by means of simulation.

Multicore Digital Signal Processors (DSPs) have gained relevance in recent years due to the emergence of data-intensive applications, such as wireless communications and multimedia processing on mobile devices, which demand increased computational performance at a low cost and power consumption. Programming these platforms is still a big challenge, posing a multitude of software design issues. In this paper, we present a toolflow to guide developers in the process of programming multicore DSPs. We evaluate the applicability of our approach by parallelizing a set of realistic embedded benchmarks on a commercial multicore DSP platform from Texas Instruments.

Early design decisions such as architectural class and instruction set selection largely determine the performance and energy consumption of application specific processors (ASIPs). However, making decisions that effectively reflect in high performance require that a careful analysis of the target application is done by an experienced designer. Such process is extremely time consuming, and a confirmation that the processor meets the application requirements can only be extracted after costly architectural implementation, synthesis and simulation. To shorten design times, this work couples High-Level Synthesis (HLS) with pre-architectural performance estimation. We do so with the aim of providing designers with an initial architectural seed together with quantitative feedback about its performance. This enables to perform a light-weight refinement process based on the obtained feedback, such that time-consuming microarchitectural implementation is done only once at the end of the refinement steps. We employed our flow to generate four potential ASIPs for a 1024-point FFT. Estimates validation and gain evaluation is performed on actual ASIP implementations, which achieve performance gains of up to 8.42x and energy gains up to 1.32x over an existing VLIW processor.

The growing complexity of modern embedded systems poses a challenge to designers of virtual platforms, as the increasing number of processors causes simulation speed to degrade. To remain viable as design tools, virtual platforms must use highly abstracted modeling levels or deploy parallel simulation technologies to keep performance up. With multi-core PC workstations being widely available today, parallel simulation seems an attractive solution. However, the introduction of concurrency into a virtual platform simulator complicates the construction of synchronization mechanisms of the simulated models. Therefore, this work presents a modeling approach for concurrent LL/SC based on SystemC/TLM. This facilitated the construction of a parallel simulator for a quad-core OpenRISC based system, gaining a performance speedup of 3.4x over a regular sequential simulator.

A scalable and highly efficient numerical linear algebra kernel mapping for coarse-grained reconfigurable architectures is proposed and applied to a 3D reconfigurable architecture, Layers, which exploits functional parallelism and a functional reconfiguration-based programming model to achieve flexibility, scalability and low energy. Instead of solving the complex problem of mapping an application to fit architectural constraints, in our approach we tailor the mapping scheme for efficiency and scalability and exploit architectural flexibility and reconfigurability to adapt the architecture to match the derived mapping. Thus, kernel execution reaches asymptotically optimal efficiency for various architectural parameters and input matrix sizes, without modification of the derived mapping. Detailed performance and power evaluations were done with input data sets with matrix sizes ranging from 64×64 to 16384×16384. Twelve architectural variants with up to 10×10 processing elements were used to explore scalability of the mapping and the architecture, achieving <10% energy increase for architectures up to 8×8 PEs, coupled with performance speed-ups of more than an order of magnitude.

Maintaining security in wireless systems has been a challenge due to the broadcast nature of wireless communication channels. Many methods have been proposed as countermeasures to eavesdropping attacks, which stand as one of the most important secrecy attack types that use the vulnerabilities of wireless channels. The majority of these methods come with the cost of additional power consumption for maintaining secrecy. In order to provide a framework that can enable a tradeoff between energy efficiency and secrecy, we provide a flexible adaptive physical layer security approach that enables tunable security levels for distinct bit streams of a single user. Our main motivation stems from the fact that not all data bits within a single bit steam require the same amount of security. The proposed adaptive power optimization framework allows the assignment of different secrecy rate constraints for distinct data streams. Via simulations, we show that the proposed approach can increase the power efficiency compared to the non-adaptive physical layer security solution, while satisfying the required secrecy constraints.

We consider in this paper the physical layer security in multi-user massive multiple-input multiple-output (MU-Massive-MIMO) system, where an eavesdropper (Eve) is assumed to be able to intercept the information intended to any of the users. Distributed antenna sets, commonly known as remote radio heads (RRHs), are deployed at the base station, which enables autonomous power allocation between the information signal and artificial noise (AN) at each antenna set. Assuming a large number of antennas at each RRH and cooperative downlink maximum-ratio transmission beamforming, we first derive the closed-form deterministic equivalents of post-processing signal to interference-plus-noise ratio (SINR) of users and Eve in both the centralized and autonomous full transmission schemes. Then, we maximize the minimum user SINR over the signal and AN powers subject to the sum power and Eve SINR constraints. The optimization in the former scheme leads to a linear programming problem, while the latter results in a complementary geometric programming (GP), which has to be transformed into an ordinary GP problem in order to be solved efficiently. Numerical results demonstrate the significance of deploying the RRHs as well as autonomous power allocation to improve the user SINR along with the secure communication with QoS guarantee in MU-Massive-MIMO.

In this paper, we present a novel algorithm for oscillator phase noise estimation using two key properties of the phase noise process in digital baseband: reduced-dimensional characteristics when expanded with Karhunen-Loeve basis functions and statistical improperness of the phase noise coefficients paving the way for the optimality of widely-linear (WL) estimators. The proposed methods are designed to take full- advantage of the second-order statistics, rank-deficient models and has an attractive trade- off between performance and complexity. To compute rank-reduced WL Wiener filter for highly compressed estimation, two methods are derived and analyzed using either data or parameter subspace reduction. Numerical experiments are presented for practically relevant phase noise distributions and they demonstrate the applicability of the proposed methods. They show that WL estimator can achieve up to 5 dB improvement over the best strictly linear estimator, with the maximum achieved in complexity-favorable low-rank conditions.

Physical layer security in the presence of passive eavesdroppers (i.e., the eavesdroppers' channels are unknown to the transmitter) in correlated channels is addressed. The majority of the literature with passive eavesdroppers assumption focus on uncorrelated channels and random artificial noise (AN) generation in the null space of the legitimate channel. This paper targets joint optimization of the AN vector and the power fraction used for beamforming in correlated channels. These two variables are obtained by maximizing the minimum secure probability of attaining a pre-determined secrecy level for a certain number of the most dangerous potential Eves, which are obtained by the correlation map. The correlation map contains long-term channel correlation matrices for all the potential Eves' locations, which are captured by legitimate users passing through these areas in the past. We use a secure probability map to illustrate the secrecy levels for all the possible positions of the legitimate user. The results show the significant secrecy enhancement of our proposed algorithm when compared to the exiting AN generation methods.

Millimeter wave (mmWave) band is characterized by very high path loss. To overcome this, spatial multiplexing and beamforming can be employed and in mmWave due to the small wavelength, large antenna arrays can be used to provide the required gain. However, unlike the traditional microwave systems it is not feasible to afford one RF chain per antenna. To overcome this practical limitation, hybrid beamforming can be utilized and the complexity of the transceiver can be reduced by implementing the RF domain processing using only the analog phase shifters. In this paper, we propose a two step approach to design a hybrid beamforming architecture. In this approach, we first design the baseband beamforming and then the RF domain beamforming is realized using an iterative algorithm. Finally, the proposed algorithm is validated by providing numerical examples by means of simulation.

In this paper, we analyze the effects of oscillator phase noise and doubly-selective fading channel on the performance of the staggered multitone (SMT) system. Unlike the more familiar discrete multitone (DMT) systems, SMT is shown to be insensitive to self-interference effects due to phase noise. The impeding channel and phase noise interference coefficients are defined and theoretical expressions for the inter-carrier and intersymbol interference are derived to establish solid analytical basis. We demonstrate the resilience of SMT waveform to phase noise distortion and channel fading effects in numerical experiments using appropriate models and the theoretical considerations are shown to fit well with simulation findings. Our assessment indicates that SMT system performs nearly as well as the classical DMT modulation for non-dispersive channels, while it outperforms DMT system by 2 dB for the studied fading channel scenario and fixed equalization complexity for both systems.

This paper presents a novel physical layer secrecy enhancement technique for multicarrier communications based on dynamic filter hopping. Using the Filter Bank Multicarrier (FBMC) waveform, an efficient eavesdropping mitigation technique is developed using time- and frequency-varying prototype filters. Without knowledge of the filter assignment pattern, an eavesdropper will experience a high level of inter-carrier (ICI) and inter-symbol interference (ISI). With this severe receive signal-to-interference-plus-noise ratio (SINR) degradation for an illegitimate receiver, the secrecy capacity of the communication system is increased. At the same time, the interference at the legitimate receiver is designed to be negligible in comparison to the channel noise.

The combination of software flexibility and hardware configurability makes partially reconfigurable application-specific instruction-set processor (rASIP) an attractive architecture, which matches the needs of computation-intensive and fast-evolving wireless receiver algorithms. This paper describes the design of a multimode multiple-input-multiple-output (MIMO) detector by using rASIP, which supports multiple MIMO detection algorithms with different antenna and modulation configurations. The rASIP is mainly constructed using a coarse-grained reconfigurable architecture (CGRA) coupled with a processor. In MIMO detection, some important computation steps (e.g., preprocessing) or even the whole detection algorithm is realized using matrix operations. Therefore, for the rASIP, the CGRA is designed to efficiently support different matrix operations used in MIMO detection, and the processor is integrated with special instructions to implement the control path required by different algorithms. Feasibility of the proposed approach is shown by implementing three noniterative MIMO detection algorithms. To evaluate the flexibility of the proposed approach, a Markov Chain Monte Carlo based MIMO detection is also realized by mapping part of the algorithm by using matrix operations on the CGRA. Postlayout results of the rASIP are generated for the implemented detection algorithms on a 65-nm CMOS technology. Compared with some selected designs based on programmable architectures and dedicated application-specified integrated circuits (ASICs), we show that following the proposed approach, the rASIP-based multimode MIMO detection, is about 1.6-5.4 times more efficient than the programmable architectures, and it approaches the throughput performance to the dedicated ASICs.

Real-time identification of connected regions of pixels in large (e.g. FullHD) frames is a mandatory and expensive step in many computer vision applications that are becoming increasingly popular in embedded mobile devices such as smart-phones, tablets and head mounted devices. Standard off-the-shelf embedded processors are not yet able to cope with the performance/flexibility trade-offs required by such applications. Therefore, in this work we present an Application Specific Instruction Set Processor (ASIP) tailored to concurrently execute thresholding, connected components labeling and basic feature extraction of image frames. The proposed architecture is capable to cope with frame complexities ranging from QCIF to FullHD frames with 1 to 4 bytes-per-pixel formats, while achieving an average frame rate of 30 frames-per-second (fps). Synthesis was performed for a standard 65nm CMOS library, obtaining an operating frequency of 350MHz and 2.1mm2area. Moreover, evaluations were conducted both on typical and synthetic data sets, in order to thoroughly assess the achievable performance. Finally, an entire planar-marker based augmented reality application was developed and simulated for the ASIP.

Writing correct parallel software for modern multiprocessor systems-on-chip (MPSoCs) is a complicated task. Programmers can rarely anticipate all possible external and internal interactions in complex concurrent systems. Concurrency bugs originating from races and improper synchronization are difficult to understand and reproduce. Furthermore, traditional debug and verification practices for embedded systems lack support to address this issue efficiently. For instance, programmers still need to step through several executions until finding a buggy state or analyze complex traces, which results in productivity losses. This paper proposes a new debug approach for MPSoCs that combines dynamic analysis and the benefits of virtual platforms. All in all, it (i) enables automatic exploration of SW behavior, (ii) identifies problematic concurrent interactions, (iii) provokes possibly erroneous executions and, ultimately, (iv) detects concurrency bugs. The approach is demonstrated on an industrial-strength virtual platform with a full Linux operating system and real-world parallel benchmarks.

With the availability of advanced MPSoC and emerging Dynamic RAM (DRAM) interface technologies, an optimal allocation of logical data buffers to physical memory cannot be handled manually anymore due to the huge design space. An allocation does not only need to decide between an on-or off-chip memory, but also needs to take an increasing number of available memory channels, different bandwidth capacities and several routing possibilities into account. We formalize this problem and introduce a Mixed Integer Linear Programming (MILP) model based on two different optimization criteria. We implement the MILP model into a retargetable tool and present a case study with representative data of the Long-Term-Evolution (LTE) standard to show the real-life applicability of our approach.

With increasing system size and complexity, designers of embedded systems face the challenge of efficiently simulating these systems in order to enable target specific software development and design space exploration as early as possible. Today's multicore workstations offer enormous computational power, but traditional simulation engines like the OSCI SystemC kernel only operate on a single thread, thereby leaving a lot of computational potential unused. Most modern embedded system designs include multiple processors. This work proposes SCope, a SystemC kernel that aims at exploiting the inherent parallelism of such systems by simulating the processors on different threads. A lookahead mechanism is employed to reduce the required synchronization between the simulation threads, thereby further increasing simulation speed. The virtual prototype of the European FP7 project EURETILE system simulator is used as demonstrator for the proposed work, showing a speedup of 4.01× on a four core host system compared to sequential simulation.

A novel class of linear soft-input soft-output detectors featuring boosted communications performance is introduced. Compared to state-of-the-art linear detectors, the detector has an SNR gain of up to 2.4 dB. We shortly summarize the algorithm, and sketch a suitable architecture. The corresponding ASIC implementation shows the feasibility and efficiency of the concept. It achieves the IEEE 802.11n standard's peak data rate of 600 Mbit/s.

A novel reduced-complexity soft-input soft-output minimum mean square error detection algorithm for MIMO systems together with an area-throughput efficient VLSI architecture is described. A detailed comparison to related work is presented. The proposed VLSI architecture of the novel algorithm represents - to the best of our knowledge - the most area-throughput efficient SISO MIMO detector ASIC reported so far, being 2.3x more efficient than its best competitor. It achieves a throughput of up to 923 Mbit/s and occupies down to half of the competitor's area while sustaining the IEEE 802.11n standard's peak data rate.

In the current literature considering multi-cell multi-user massive multiple-input multiple-output (MU-Massive-MIMO) systems, equal uplink power allocation among users is typically assumed, which does not exploit the potential of peruser power control. By contrast, in this paper we apply multi-cell uplink power control, assuming the minimum mean-square-error receiver based on the pilot contaminated channel estimation and a very large but finite number of antennas at the base station. We derive the lower bound on the average post-processing uplink signal to interference-plus-noise ratio (SINR) with individual power assignment between pilot and data transmissions for each user, which facilitates a joint iterative uplink pilot and data power control strategy that minimizes the sum transmit power of all users subject to the per-user SINR and per-user power constraints. The convergence of the proposed algorithm to a unique fixed point optimal solution is discussed for both single- and multi-user scenarios. Numerical results indicate the significance of uplink power control which further improves the energy efficiency in MU-Massive-MIMO systems.

A computational complexity analysis of matrix inversion used in soft-input soft-output minimum mean square error (MMSE) MIMO detectors and a comprehensive literature comparison of corresponding VLSI implementations are presented. They indicate that the application specific integrated circuit (ASIC) proposed in this paper is - to the best of our knowledge - the most area-throughput efficient VLSI architecture reported so far, outperforming the second best by a factor of 1.7×. The ASIC achieves the IEEE 802.11n standard's peak data rate of 600 Mbit/s.

Staggered multitone (SMT) modulation scheme has received a considerable attention recently due to its higher spectral efficiency compared to the conventional OFDM systems and robustness to frequency offset and Doppler spread. However, channel equalization in SMT is complicated by the so called intrinsic interference as a result of non-flat channel response in each subchannel. In the presence of I/Q imbalance (IQI), this task becomes even more challenging as the image band and its intrinsic neighborhood contaminates the received signal. This paper deals with widely linear schemes for the effective channel equalization using time-domain and frequency-domain methodologies. Further iterative improvements are proposed for the later, combining enhanced equalization with per-subchannel-pair processing after intrinsic interference cancellation. The proposed techniques are simulated for both the uncoded and coded systems suffering from frequency-selective IQI and their effectiveness with multipath channels is demonstrated.

Early design space exploration at Electronic System Level (ESL) can be done either using untimed functional models, timed functional models or performance models, which use random or zero data instead of the actual data. In order to be applicable to the two latter types, ESL power estimation approaches often rely only on sub-block activity information. This work shows the benefit of additionally using the switching activity information of actual data available in timed functional models for power estimation. A case study shows that a considerable gain in accuracy can be achieved while causing only a moderate simulation slowdown.

Little consideration has so far been dedicated to the investigation of the implementation complexity of stochastic detectors for multi-antenna (MIMO) systems although they promise communications performance close to max-log detection for certain SNR regimes. In this work, we propose a complete redesign of the only reported parallel VLSI architecture for soft-input soft-output Markov chain Monte Carlo based MIMO detection to date. Using multiplier-free Gibbs Sampler implemen-tations, dynamic scaling of the noise density and multiple further architectural optimizations, we significantly reduce the area and improve the timing, yielding AT-efficiency improvements of as much as 3.6 times.

This paper targets the joint optimization of the signal-to-interference-plus-noise ratio (SINR) and secrecy in wireless networks. Although the optimization of the SINR with beamforming in wireless networks is well known, the joint optimization of the secrecy and the SINR of the users is a new problem which gets a high relevance recently. The optimization problems investigated in this paper are based on the joint optimization of the beamforming vectors and transmit powers. This paper presents closed form solutions for two optimization approaches for a simple power control scenario with a single user and a single eavesdropper. Two approaches are distinguished: beamforming without artificial interference (AI) and beamforming with AI. For both approaches, this paper investigates a max-min based beamforming problem and a minimum eavesdropper SINR problem with an SINR constraint for the legitimate receiver.

This paper proposes a novel matched filter optimization based approach to improve secrecy in a communication among two legitimate users. The presented optimization scheme, named as QoS-based filter design, minimizes the stop-band attenuation and uses quality-of- service constraints on the legitimate receiver and an eavesdropper. The resulting problem is relaxed to a convex problem. The filter coefficients are optimal regarding the legitimate receiver's matched filter auto-correlation function, however, it results in a sub-optimal filter for the eavesdropper secrecy constraints. Therefore, an additional post-processing is developed to match the secrecy constraints.

Channel frequency and spatial correlation are essential for adaptive channel prediction, which enables flexible scheduling. This correlation information is determined by the environment and can be learned and stored in a map to avoid online tracking. In this paper we propose a method to generate a channel frequency-spatial correlation map from the measurement campaign. Only two position-dependent parameters are stored in the map and the spatial atuocorrelations of the parameters are examined to interpolate channel correlation for the unmeasured positions. Adaptive unbiased prediction of channel gain based on the correlation map is used to compensate the outdated channel state information. The performance of flexible modulation and coding schemes using the distribution of predicted channel gain is shown through numerical simulation.

I/Q imbalance (IQI) is one of the major front-end imperfections affecting the performance of communication systems. Due to frequency-dependent (FD) IQI, channel is elongated and is split into direct and image channels. We consider the problem of joint estimation of the channel and I/Q parameters for OFDM based systems. Time-domain estimation of the effective channel taps poses a question: what is the optimal number of taps that need to be estimated for the best estimation performance? More the estimated taps, more is the noise contribution to the estimator. Lesser the estimated taps, less is the precision due to unestimated taps. In this paper, we address this issue by deriving analytic expressions for mean squared errors (MSE) of estimates of the effective channels and conditions for their optimization. In the absence of channel knowledge, we propose a choice of number of taps to improve estimation performance.

This paper deals with the optimization of the multiuser (MU) pilot design for orthogonal-frequency-division-multiple-access (OFDMA) systems perturbed by the I/Q imbalance (IQI) impairment. For the frequency-selective Rayleigh propagation channels, the proposed approach exploits the decoupled direct and image channels, and the knowledge of the effective channel statistics to realize dual linear-minimum-mean-square-error (LMMSE) channel estimators. We develop the pilot power distribution and positioning approach for the training sequence design under the channel mean-square-error (MSE) minimization criterion considering the existence of IQI and guard bands. For the pilot power allocation, we formulate the problem into semi-definite programming whereas positions are assigned with either a heuristic greedy method or fairness instigating genetic combinatorial optimization. Simulation results indicate that with the proposed pilot design, it is possible to achieve a better MSE performance than the conventional MU channel estimation methods and introduce user fairness when selecting pilot composition from the shared pool of resources.

Due to limited cooperation between the primary users and the secondary users (SUs) in practical spectrum sharing systems, the secondary transmitters and receivers are assumed to have partial channel state information related to the primary receiver. Under such an assumption, this work investigates power allocation strategies for the SUs subject to an outage probability constraint on the primary transmission and a peak transmit power constraint on the secondary transmission. The challenge lies in the non-convexity of the outage probability constraint. Firstly, we prove that strong duality holds and that the Karush-Kuhn-Tucker (KKT) conditions are necessary for optimality. The optimal solution is then derived by addressing the optimality issues of the KKT solutions. Secondly, in order to further reduce the algorithmic complexity, two suboptimal strategies are proposed. The first one is designed based on several simplifications of the optimal strategy. The second one is derived from the convex relaxation of the non-convex primal problem, which corresponds to the problem with the conventional interference temperature constraint. The performance for both suboptimal strategies is derived in closed form. All proposed strategies are shown to outperform non-adaptive power transmission. The near-optimality of the two suboptimal strategies is also validated, in particular for the first one.

Architects and developers use virtual prototypes of computer systems to receive early feedback on hardware design decisions as well as to develop and debug system software. This is facilitated by the comprehensive inspection capabilities virtual prototypes offer. For virtual prototypes, execution speed is crucial to support the users' productivity. Parallel simulation techniques are employed to offset the speed impact of the increasing number of cores that need to be simulated in virtual prototypes of parallel and embedded systems. SystemC is the de facto industry standard library for virtual platform modeling. Since currently no parallel SystemC library is commonly available, typical SystemC models are coded for execution in sequential simulation environments. Simply putting such models into parallel simulators may lead to thread-safety issues and may additionally cause nondeterministic simulator behavior. This article proposes a methodology to support simulation creators to face the challenge of integrating such legacy models into parallel SystemC environments. The feasibility of the proposed method is evaluated by parallelizing the latest instance of the EU FP7 project EURETILE embedded platform simulator. Using legaSCi , on four host processor cores a speedup of 2.13× is demonstrated, without having to change the individual models of the simulator.

In this paper, we have presented a Reconfigurable Application-specific Instruction-set Processor (rASIP) that processes mixed-radix(2, 4) 64 and 128-point Fast Fourier Transform (FFT) algorithms while satisfying the partial execution-time requirements of IEEE-802.11n standard. The rASIP was designed by integrating a template-based Coarse-Grain Reconfigurable Array (CGRA) in the datapath of a simple Reduced Instruction-Set Computing (RISC) Processor. The instruction set of the RISC processor was extended to add special instructions to enable cycle-accurate processing by the CGRA. The rASIP is synthesized for Field Programmable Gate Arrays for the measurement of resource utilization and execution time. The postfit gate-level netlist of rASIP was simulated to estimate the power and energy consumption. Based on our measurements and estimates, we have studied the advantages of using rASIP in comparison with other systems.

Power consumption is an important factor in chip design. The fundamental design decisions drawn during early design space exploration at electronic system level (ESL) have a large impact on the power consumption. This requires to estimate power already at ESL, which is usually not possible using standard ESL component libraries due to missing power models. This work proposes a methodology that allows extension of ESL models with a power model and to automatically calibrate it to match a power trace obtained by gate-level simulation or measurements. Two case studies show that the methodology is suitable even for complex communication architectures.

The fast evolving applications in modern digital signal processing have an increasing demand for components which have high computational power and energy efficiency without compromising the flexibility. Embedded FPGA, which is the customized FPGA with heterogeneous fine-grained application specific operations and routing resources, has shown significantly improved efficiency in terms of throughput, power dissipation and chip area for the target application domain. On the other hand, the complexity of such architecture makes it difficult to perform an efficient architecture exploration and application synthesis without tool support. In this work, we propose a framework for the design of embedded FPGA (eFPGA) architectures, which is extended from an existing framework for Coarse-Grained Reconfigurable Architectures (CGRAs). The framework is composed of a high-level modeling formalism for eFPGAs to explore the mapping space, and a retargetable application synthesis flow. To enable fast design space exploration, a force-directed placement algorithm is proposed. Finally, we demonstrate the efficacy of this framework with demanding application kernels.

Multiple-input multiple-output (MIMO) wireless transmission together with iterative decoding at the receiver is a key technique to achieve high spectral efficiency. However, particularly the required soft-input soft-output (SISO) MIMO detector entails a very high complexity, which motivates the investigation of suboptimal detectors with reduced complexity. In this paper, we present-to the best of our knowledge-the first implementation of a parallel VLSI architecture for a SISO detector based on Markov chain Monte Carlo (MCMC) methods. The proposed architecture is scalable and allows to exploit the parallelism inherent in the considered MCMC algorithm. We investigate the implementation costs and show that this architecture covers a wide range of trade-offs between throughput and silicon area.

This paper considers the conventional eigenvalue decomposition (EVD) based and widely linear (WL) channel estimations to alleviate inherent pilot contamination problems in multi-cell multi-user massive multiple-input multiple-output (MU-Massive-MIMO) systems. Both channel estimation schemes utilize the asymptotic orthogonality between the propagation vectors of different users which would be true only if the number of base station (BS) antennas goes to infinity. However, the limit on the number of BS antennas plus the error on the sample-based covariance matrix of the received signal deteriorate the channel estimate in practice. We derive therefore the closed-form mean-square-error (MSE) of both channel estimates characterizing two aforementioned error sources, which analytically demonstrates that the WL algorithm is superior to the EVD-based one in two folds: it applies more orthogonalized real representations of channel vectors and reduces a typical phase shift in EVD-based estimate to a sign ambiguity. The performance analysis is verified by our numerical results.

Offset-QAM (OQAM) based OFDM has been considered as a promising technique for future wireless networks due to its higher resilience to narrow-band interference and doubly dispersive channels. In this paper, we investigate the effects of the RX imperfections, namely the I/Q imbalance (IQI) and the carrier frequency offset (CFO), on OFDM/OQAM downlink performance coupled with the imperfect knowledge of the frequency-selective channel. The influence of each impairment is characterized by the interference analysis of the demodulated signal that reveals interesting insight into the distortion origination. Then, we analytically investigate the performance loss as a function of IQI, CFO and channel distortions in a realistic receiver with channel estimation error. To cope with impaired reception, a joint maximum-likelihood estimation method with repetitive training signals is employed. Simulation results demonstrate the relative sensitivity of OFDM/OQAM receivers to the impairments and that the performance loss due to the imperfections can be recovered by the compensation technique.

In this paper we propose a handover prediction algorithm based on signal-to-interference-and-noise-ratio (SINR) maps. Because SINR values at a user are dependent on geographical positions if the transmission powers of base stations (BS) are known, we introduce the concept of a SINR map which is a geographical map with overlay average SINR values at users at map pixels. The handover position is predicted by maximizing the probability function of positions along the street with handover thresholds based on the SINR map with considering fast fading characteristics while the handover timing is predicted by mobility prediction. The result of handover prediction is shown to be consistent with the simulated real handover very well. Combined with handover prediction and SINR maps the near-future user and channel conditions can be predicted, which enable the long-term window scheduling algorithm with proportional fairness constraint among users in multicell multiuser orthogonal frequency division multiplexing (OFDM) systems with handover management. We show that the proposed algorithm outperforms previous instantaneous scheduling algorithms in terms of sum rate significantly.

This paper presents a low complexity sub-optimal algorithm for the max-min beamforming problem (MBP) in multicell multicast transmission in heterogeneous networks. The beam pattern is jointly optimized for all users inside a cell in a multicell scenario such that the signal-to-interference-plus-noise ratio (SINR) of the worst users is maximized subject to per-base station power constraints. The presented algorithm is based on an uplink-downlink duality framework derived by Lagrangian duality theory. The algorithm has similarities to a recent solution derived for the MBP with a unicast transmission. Compared to the standard semidefinite relaxation based bisection algorithm, the new approach is based on a linear program which is less complex compared to a semidefinite program.

Uplink minimum mean-square-error (MMSE) detection in multi-user multiple-input multiple-output (MU-MIMO) systems with multi-cell setup is investigated in this paper. We first derive a closed form lower bound on the ergodic achievable uplink rate for each user, assuming perfect channel state information available at the base station.We further analyze and compare the asymptotic performance of an uplink with multi-cell MMSE based detection to its special case of single-cell MMSE detection. The analysis results indicate that the use of large number of base station antennas in multi-cell MU-MIMO systems leads to an increase of energy and spectral efficiency. Our analysis is based on results from random matrix theory and is verified by the simulations.

This paper presents a blind method to resolve imbalances between I and Q paths in low-IF receivers. In particular, we investigate the mismatch arising from the coefficient variation of the complex filters that leads to the frequency-selective imbalance problem. The key point in the proposed novel DSP-based solution is the transformation of the signals to frequency domain and the estimation of the mismatch cancellation filter based on the instantaneous separation in each frequency bin. Although this approach relaxes the original model with convolutive mismatch, it still requires long observation records to obtain a sufficient performance. The proposed method exploits the continuity property of the cancellation filter in the frequency-domain to improve the estimator performance even with short symbol block lengths. Moreover, we derive an asymptotic bound on the attainable MSE in the case of Gaussian sources and deterministic parametrization of the frequency-selective model. The numerical results under the mismatched filtering condition reveal that the interference-separation performance of the proposed method is superior to that of the conventional methods and approach the performance bound for interference-to-signal ratios of interest.

Channel correlation is usually tracked for adaptive channel estimation, prediction and network optimization. Time correlation is determined by the relative movement of the transmitter and the receiver, while frequency and spatial correlation depend on the environment layout that can be collected and stored for future use. In this paper, we introduce the concept of channel correlation map stored at the base station (BS), which adds both frequency and space direction channel correlation parameters as overlay information to a geographic map. We propose a measurement method of channel correlation maps by processing uplink transmission data and show the influence of available bandwidth on the measurement accuracy. Two application cases with the correlation map are shown through numerical simulation. One is adaptive MIMO-OFDM channel estimation without online tracking correlation parameters, the other is channel prediction for transmit scheduling and beamforming design to reduce the performance degradation due to outdated channel state information (CSI) caused by the feedback delay.

In wireless communication systems, dual-polarized (DP) instead of single-polarized (SP) multiple-input multiple-output (MIMO) transmission is used to improve the spectral efficiency under certain conditions on the channel and the signal-to-noise ratio (SNR). In order to identify these conditions, we first propose a novel channel model for DP mobile Ricean MIMO channels for which statistical channel parameters are readily obtained from a moment-based channel decomposition. Second, we derive an approximation of the mutual information (MI), which can be expressed as a function of those statistical channel parameters. Based on this approximation, we characterize the required SNR for a DP MIMO system to outperform an SP MIMO system in terms of the MI. Finally, we apply our results to channel measurements at 2.53 GHz. We find that, using the proposed channel decomposition and the approximation of the MI, we are able to reproduce the SNR values above which DP MIMO systems outperform SP MIMO systems.

Processor Systems on Chip (MPSoCs) in order to cope with the increasing applications demands and the tight energy budget of portable devices. The complexity of these systems makes them difficult to program, which has caused academia and industry to look for alternative methodologies and models. In the particular case of multimedia and baseband processing, dataflow models are being proposed and appear to be a sensible choice to represent applications. While high-level models, like dataflow, increase programmers' productivity, new, powerful tools are badly required that lower the abstract specification into an efficient implementation. In this paper, a framework is presented that provides support for mapping multiple dataflow applications onto heterogeneous MPSoCs. The framework is aware of design constraints, provides different means for performance estimation and supports a variety of mapping heuristics. The tool is showcased on three applications on a virtual platform containing heterogeneous processing elements. The heuristics for single applications reported a speedup of up to 40% when compared against random walk. The multi-application component helped to find an appropriate scheduling configuration that met real-time constraints when the three applications were running simultaneously.

This paper investigates power allocation strategies for secondary users (SUs) in cross-interfering spectrum sharing systems. Addressing limited cooperation between primary users (PUs) and SUs, only instantaneous channel state information (CSi) of the secondary link and statistical CS! of the other links is assumed to be available at the secondary transmitters (STs). We aim at maximizing the secondary achievable rate subject to both a peak power constraint at the ST and an average interference power constraint at the primary receiver. First, the optimal power control strategy is developed. !n order to reduce the complexity, two suboptimal optimization strategies are proposed. The first one, named double threshold waterfilling (DT-WF), is based on an approximation of the optimal solution. The second strategy, named double threshold constant-power waterfilling (DTCP-WF), further simplifies DT-WF. Additionally, the achievable performance is derived in closed form for both suboptimal strategies. We also discuss the algorithm design in the multiple primary links scenario. Numerical results show the effectiveness of the proposed strategies and validate the accuracy of the closed-form analysis.

Kahn Process Networks (KPNs) are a widely accepted programming model for MPSoCs. Existing KPN mapping techniques mainly focus on assigning processes to processors. However, with embedded interconnect becoming more complex, communication has started to play an equally important role to that of computation. This paper presents a new KPN mapping algorithm that addresses communication and computation jointly. The algorithm is tested on two platforms with real applications and with randomly generated KPNs. We show that the algorithm finds solutions in situations where bare process mapping fails. It also reduced the average application makespan considerably when compared to previous heuristics.

Full-system simulators are essential to enable early software development and increase the MPSoC programming productivity, however, their speed is limited by the speed of processor models. Although hybrid processor simulators provide native execution speed and target architecture visibility, their use for modern multi-core OSs and parallel software is restricted due to dynamic temporal and state decoupling side effects. This work analyzes the decoupling effects caused by hybridization and presents a novel synchronization technique which enables full-system hybrid simulation for modern MPSoC software. Experimental results show speed-ups from 2x to 45x over instruction-accurate simulation while still attaining functional correctness.

Due to their good flexibility-performance trade-off, Application Specific Instruction-set Processors (ASIPs) have been identified as a valuable component in modern embedded systems, especially the extensible ones, achieving good cost-efficiency trade-offs. Since the generation of the described hardware is usually automated to a high extent, in order to deliver an ASIP-based design in due time, developers are limited by the performance of the underlying simulation techniques for software development. On the other hand, the Hybrid Processor simulation technology (HySim), which enables dynamic run-time switching between native and instruction-accurate simulation, has reported high speed-up values for some fixed architectures. This paper presents enhanced HySim technology for extensible cores, based on a layered simulation infrastructure. This technology has shown a speed-up on a per-function basis of two orders of magnitude for a realistic MIMO OFDM benchmark on a multi-core platform with customized Xtensa cores by Tensilica.

This paper describes the implementation of a multi-mode MIMO detector based on the concept of partially reconfigurable ASIP (rASIP). The multi-mode detector can support three different detection algorithms which are the Maximum Ratio Combining, the linear Minimum Mean Square Error (MMSE) detection, and the MMSE Successive Interference Cancellation. The detection algorithms also support different antenna configurations and modulation schemes. The rASIP is based on a Coarse-Grained Reconfigurable Architecture (CGRA), which is designed for efficient architectural support of matrix operations. A matrix inversion algorithm, which is used for the preprocessing of different detection algorithms, is mapped on the CGRA. By integrating a processor with the CGRA, the variations in the control path of different algorithm configurations can be handled efficiently. To the best of our knowledge, we show, for the first time that, a CGRA-based multi-mode MIMO detection is extremely efficient and matches the performance of dedicated ASIC implementation.

Due to limited cooperation between the primary users and the secondary users (SUs), the SUs only have partial channel state information related to the primary receiver. Under such an assumption, this paper investigates power allocation strategies for the SUs in spectrum sharing systems subject to an outage probability constraint on the primary transmission and a peak transmit power constraint on the secondary transmission. The challenge lies in the non-convexity of the outage probability constraint. We investigate two methods to solve the non-convex optimization problem. First, strong duality is shown to be satisfied. Since the Karush-Kuhn-Tucker (KKT) conditions are then necessary but not sufficient for optimality, we derive the KKT solutions and address the optimality issue of the solutions. Alternatively, the non-convex constraint is replaced by a stricter convex constraint. A more conservative suboptimal solution is thus obtained, which corresponds to the solution of the problem with the conventional interference temperature constraint. Simulation results show that both proposed strategies outperform constant-power transmission. The superiority of the optimal strategy over the suboptimal one is also verified.

Dual-polarized (DP) multiple-input multiple-output (MIMO) systems are known to be beneficial in terms of the spectral efficiency under certain conditions on the channel and the signal-to-noise ratio (SNR). In order to assess under which conditions DP antenna setups are advantageous over single-polarized (SP) antenna setups, an accurate yet analytically tractable modeling of such channels is a necessary but challenging task. We propose a novel channel model for DP mobile Ricean MIMO channels for which the statistical channel parameters are readily obtained from a moment-based channel decomposition. An approximate evaluation of the mutual information (MI), expressed as a function of the statistical channel parameters of the proposed channel model, is derived. This approximation allows to assess when it is beneficial in terms of the MI to switch from an SP to a DP setup. Finally, we evaluate the MI for selected SP and DP setups based on channel measurements at 2.53 GHz. We find that the DP setup only provides an improvement in terms of the MI in medium- to high-K-factor scenarios above a certain SNR. The approximate evaluation of the MI is able to accurately reproduce the SNR at which one should switch from an SP to the DP setup.

When an iterative receiver has more than one iteration loop, scheduling the iterative decoding process is an important issue. To find the optimal scheduling, extrinsic information transfer (EXIT) function was the main tool in the literature. However, it is only very efficient when the codeword is significantly long. In this paper, under the consideration of a packet-based transmission scenario, we propose modeling the scheduling search problem as the foraging problem of ant colony. And then, an ant colony optimization (ACO) algorithm, labeled as max-min ant system (MMAS), is adopted and tailored for our problem. Simulation results show MMAS outperforms the EXIT function-based method when practical length codewords are used.

We propose a general channel model for mobile Ricean multiple-input multiple-output (MIMO) channels, which is characterized by parameters that are readily obtainable from measurements. To this end, a moment-based channel decomposition is derived. For the case of statistical channel state information (CSI) at the transmitter (TX) and instantaneous CSI at the receiver, we derive an approximation of the achievable rate, i.e., the mutual information (MI), which is only a function of the channel parameters of the proposed channel model and thus gives insight into the parameters that influence the MI. Finally, we evaluate the MI for a 4 × 4 MIMO system based on channel measurements at 2.53 GHz for two low-complexity TX strategies, i.e., a beamforming (BF) and a spatial multiplexing (SM) strategy. We find that the proposed channel model and the approximate evaluation of the MI are both accurate for realistic signal-to-noise ratio (SNR) values. The approximate evaluation is able to reproduce crossing points between the MI of the considered TX strategies; it thus reflects the SNR at which one should switch from the BF to the SM strategy.

VLSI implementations for iterative channel estimation in MIMO-OFDM systems are a challenge for future receivers. Additionally sufficient flexibility is required to support multi-standard multi-mode operation. These challenges are investigated in this paper by two VLSI implementations for a MIMO-OFDM decision directed channel estimation (DDCE) algorithm: The first application specific integrated circuit (ASIC) implementation for simplified decision directed (SIDD) MIMO-OFDM channel estimation and a custom vector processor running a SIDD software implementation. This work shows that the software implementation of the SIDD algorithm on a custom vector processor can compete with the ASIC implementation. Both implementations and the efficiency/flexibility trade-offs are analyzed quantitatively.

The extension of multiple-input multiple-output (MIMO) systems to the polarization domain is known to have potential benefits in terms of the spectral efficiency. It is thus of importance to understand how the channel influences the spectral efficiency, e.g., when a dual-polarized (DP) antenna setup should be favored over a single-polarized (SP) one. In this work, we study the achievable rate, i.e., the sum mutual information (MI) of all transmitted streams, over DP MIMO channels with linear receivers. We derive an approximation of the sum MI with a linear minimum mean squared error (LMMSE) or a zero forcing receiver which is an explicit function of statistical channel parameters. The evaluations of selected 4×4 SP and DP MIMO setups are based on channel measurements performed at 2.53 GHz in an urban macrocell scenario. The results reveal that DP antenna setups can yield substantial gains in the sum MI on links with high K-factors and high signal-to-noise ratios (SNRs). Moreover, the degradation in the sum MI with two streams due to the use of an LMMSE receiver is found to be small, especially for the DP antenna setup. The approximate evaluation of the sum MI is able to reproduce the SNR threshold region in which a second transmitted stream should be activated or one should switch from an SP to a DP antenna setup.

This paper studies an optimal power allocation strategy in spectrum-sharing cognitive radio systems. In reality, it is difficult for the secondary users (SUs) to obtain perfect channel state information (CSI) related to the primary users (PUs) due to the lack of cooperation between the SUs and the PUs. We assume that only instantaneous CSI of the secondary link and statistical CSI of the other links is available to the SUs. This assumption not only reveals the realistic challenges, but also brings mathematical challenges in solving the optimization problem in closed form, since the performance evaluated with statistical CSI involves expectation operations. We reformulate the objective function in closed form and derive the optimal power allocation solution. The feasibility of the solution is discussed. Furthermore, we provide several interesting insights into the achievable performance based on the properties of the solution.

Existing mobility prediction algorithms focus on predicting the next cell or interesting regions such as a home zone. But for position- and movement-based optimization of transmission in a cell such coarse-level mobility prediction is not sufficient. In this paper a learning-based graphical model is introduced which allows a fine-level prediction of the movements and velocities of mobile users inside a cell. We divide the mobile users into different user groups by velocities and learn the path patterns and user type transitional probabilities. Based on this a-priori information a three-step mobility prediction algorithm considering positioning error and future user type is proposed. The simulation result shows a better level of prediction accuracy compared to previous methods.

This paper studies the achievable performance of a single-antenna spectrum-sharing system. Due to limited cooperation between secondary users (SUs) and primary users (PUs), perfect channel state information (CSI) related to the PUs is hard to obtain for the SUs. Therefore, we assume the secondary transmitter and receiver have only statistical CSI from the secondary transmitter to the primary receiver. First, we investigate the optimal power adaptation method under both a peak transmit power constraint and an average interference constraint. The optimal power allocation strategy is categorized into three regions based on the channel variations. Furthermore, we propose an efficient method in order to determine the optimal thresholds to divide three regions. Second, we derive closed-form expressions of the ergodic capacity of the secondary link over Rayleigh fading channels. The analytical results reveal some interesting insights into the achievable performance of the spectrum-sharing system, which are discussed and verified by simulation results.

In this paper, we derive a closed-form expression for the probability density/mass function (PDF/PMF) and the moment generating function (MGF) of the quantized detector soft output, i.e., extrinsic log-likelihood ratio (LLR), for multiple-input multiple-output (MIMO) bit-interleaved coded modulation with iterative decoding (BICM-ID) systems. The effect of either LLR clipping or LLR clipping with rounding, often applied in practical implementations, are considered. Using the derived expression, we analyze the asymptotic coded bit error rate (BER) for MIMO BICM-ID systems with the two quantization operations under a flat Rayleigh fading channel. The error rate degradation caused by quantizing the extrinsic LLR is then interpreted as an additional signal-to-noise ratio (SNR) loss. Rather than Monte Carlo simulations, this theoretical treatment provides a more convenient alternative to determining the clipping level and optimal word-length (the number of bits needed to represent signals) for LLR in a BICM-ID implementation. Finally, several other applications of this proposed theoretical analysis are also demonstrated.

Based on the Expectation Propagation framework, we derive a MIMO detector that consists of an interference cancellation (IC) step, followed by linear minimum mean square error (LMMSE) filtering. The distinguishing feature of our algorithm, compared to conventional IC-LMMSE detectors for iterative MIMO receivers, is the way how we compute the symbol statistics that are used in the IC and LMMSE steps. In an earlier publication, it has been shown empirically that full posterior feedback from the decoder to the IC-LMMSE detector can outperform the usual choice of extrinsic feedback, which seems to contradict the Turbo principle. The systematic derivation in the present paper provides an explanation of this phenomenon, and results in a further improved algorithm that outperforms the conventional IC-LMMSE detector with either extrinsic or posterior feedback. While we consider only multi-antenna systems, we note that the same principle can be applied to similar problems in signal processing, such as Turbo equalization for frequency-selective channels, or multi-user detection in CDMA systems.

This paper presents two enhancements for improving the convergence behavior of bit-interleaved coded modulation iterative decoding (BICM-ID) in multiple-input multiple-output (MIMO) systems. As typical tree search based MIMO demapping algorithms for BICM-ID are based on the suboptimal Max-Log-MAP (maximum a-posteriori) criterion, the first enhancement aims at correcting the outputs of such MIMO demappers towards the optimal Log-MAP criterion. For the second enhancement, the deterministic annealing technique is applied to the iterative decoding process. Through simulation results, the efficiency of both enhancements has been demonstrated via the decoding performance and complexity.

In this paper, we theoretically analyze the asymptotic coded bit error rate (BER) for multiple-input multiple-output bit-interleaved coded modulation (MIMO-BICM) with linear minimum mean-squared error (MMSE) detection and estimation for a flat Rayleigh fading channel. The numerical simulations validate the accuracy of our theoretical analysis. With such study, we can model the BER improvement of MMSE detection compared with zero-forcing detection as a signal-to-noise (SNR) gain.

We derive a Markov chain Monte Carlo algorithm for data detection in multi-antenna systems. The proposed algorithm is based on the Rao-Blackwellization principle, and is parameterized by a value eta that can be interpreted as a system temperature. We demonstrate by simulations that systems with increased temperature (η>;1) significantly outperform the straightforward choice of η=1. Due to its log-domain formulation, our algorithm combines near-optimal performance with low implementation complexity.

Interference is one of the major bottlenecks in current cellular networks. A realistic evaluation of the achievable performance in interference-limited systems based on measured channels is thus necessary; however, only few results are known from literature. We evaluate the achievable performance in a cellular network with inter-cell interference based on measured channels in an urban macrocell scenario at 2.53 GHz. To this end, the mutual information is introduced as an appropriate performance measure over fast and slow fading channels that are non-stationary but doubly underspread. We discuss appropriate channel normalizations and the limitations of an evaluation based on sequential measurements. Moreover, we analyze the accuracy of an approximate but commonly used evaluation of the mutual information. A second-order multivariate Taylor series expansion reveals the signal and interference contributions to the approximation error. We find that the approximation is accurate in realistic ICI scenarios.

Modern compilers parse their input, which usually is a high-level programming language, and then convert the resulting parse tree into an intermediate representation (IR). This IR has the important property of being source language and target processor independent, which allows for generalized optimizations. This flexibility, however, also discards some of the high-level properties of the source language. In this paper we present an analysis that can extract most of the control flow structures typically found in the C programming language from a medium level IR. Mirtoc is an implementation of this analysis for the specific case of CCMIR, the IR used in ACE's CoSy® compiler framework. A compiler based on mirtoc is able to emit C code that is well structured, readable by a human and can be compiled by a back end compiler with relatively low overhead. This enables the use of optimizers based on medium level IRs in a source-to-source flow.

In a network with frequency reuse-1 intercell interference(ICI) is a limiting factor. Especially cell edge users are subject to strong ICI. In long term evolution (LTE) those users can be served by multiple base stations (BSs). By using a cooperation among multiple BSs, the signal to interference and noise ratio (SINR) can be balanced. In this paper a fast (direct)solution for the SINR balancing is presented and the optimality is proven for the coherent cooperative multipoint transmission. A coherent transmission over multiple links is difficult in practice. Therefore, a non-coherent algorithm is presented as well and compared with the coherent algorithm.

This paper studies robust transceiver optimization for cognitive downlink systems in the presence of imperfect channel state information (CSI). We aim at minimizing the sum mean square error (MSE) of the secondary downlink transmission subject to the interference constraint imposed on the primary users. The MSE duality is developed to describe the uplink-downlink relation, in which imperfect CSI and multiple power constraints are taken into account. Based on the duality result, we propose an efficient robust approach which can effectively avoid the violation of the interference constraint. We also discuss the performance in terms of optimality as well as complexity issue. Compared to the downlink-based approach, the proposed one features faster convergence speed and lower complexity.

For soft-input soft-output sphere decoding (SD), the combination of the Schnorr-Euchner (SE) enumeration and the radius reduction shrink the search space quickly but with considerable computational complexity. In this paper, a low complexity approach is proposed to reduce the tree search space before SD starts. Particularly, such reduction is achieved by 1) tightening the initial radius; 2) restricting the search space to a subset of the symbol lattice. With further enhancement on the tree pruning constraint, simulation results demonstrate significant complexity savings with negligible error rate performance loss.

This paper presents a practice oriented approach for an optimization of user scheduling, base stations assignment and beamforming with multipoint transmission in a multiuser multicell scenario using statistical channel knowledge. Especially the cell edge users gain if they are served by multiple base stations (BSs). The max-min beamforming optimization balances the signal to interference and noise ratio of all scheduled users. An additional optimization of the scheduling decisions and the assignment of BSs to users can additionally improve the individual rates of the users. A multiuser multicell simulation based on the WINNER II channel model proves the enhanced performance of the presented low complexity algorithm for the network-wide optimization of the three degrees of freedom: optimal transmit beamforming, temporal user scheduling and base station to user assignment.

In practice, the imperfect channel state information can degrade the optimization performance of a cognitive system, especially yielding the detrimental violation of the interference constraint perceived by the primary users. This paper investigates the linear transceiver design in cognitive downlink systems with the imperfect channel knowledge, aiming at minimizing the mean square error of the secondary network subject to both the transmit and interference power constraints. Two methods are proposed to solve the optimization problem. The first alternating method decomposes the non-convex primal problem into two subproblems. Each of them is converted to the standard convex optimization forms. The second method is based on the reformulation of the primal problem into a two-loop optimization problem in which a more efficient gradient projected method applies. We also prove the condition to achieve Karush-Kuhn-Tucker optimality. The effectiveness and robustness of the proposed solutions are validated by the simulation result.

This paper proposes a new concept of multiple-input multiple-output (MIMO) detection, aiming at minimizing the average computational cost. The detection methods are adapted according to the estimated channel state information to deliver just-acceptable error rate (JAER) performance. Error rate models for two popular MIMO detection algorithms are derived given the channel matrix. From these models, a channel-adaptive-MIMO (CA-MIMO) receiver with detector-switching strategies is proposed. Simulation results demonstrate that the proposed CA-MIMO detector meets the JAER criterion efficiently. Compared with the sophisticated Sphere Search (SS) MIMO detector, the average saving at moderate signal-to-noise ratio (SNR) is around 58% to 72%, depending on different modulation alphabets. At high SNR, the CA-MIMO detector almost always switch to Zero-Forcing (ZF) detection, where the complexity is several orders lower than the SS detector.

Nowadays, most embedded devices need to support multiple applications running concurrently. In contrast to desktop computing, very often the set of applications is known at design time and the designer needs to assure that critical applications meet their constraints in every possible use-case. In order to do this, all possible use-cases, i.e. subset of applications running simultaneously, have to be verified thoroughly. An approach to reduce the verification effort, is to perform composability analysis which has been studied for sets of applications modeled as Synchronous Dataflow Graphs. In this paper we introduce a framework that supports a more general parallel programming model based on the Kahn Process Networks Model of Computation and integrates a complete MPSoC programming environment that includes: compiler-centric analysis, performance estimation, simulation as well as mapping and scheduling of multiple applications. In our solution, composability analysis is performed on parallel traces obtained by instrumenting the application code. A case study performed on three typical embedded applications, JPEG, GSM and MPEG-2, proved the applicability of our approach.

In an library based waveform (WF) development for software defined radios, high-level performance estimation models of implementations are beneficial for converging quickly to an optimal mapping of a WF-description to a hardware platform. A model that estimates the changes in performance, e.g. bit error rate (BER), due to the configuration-parameters, e.g. input datawidth, in implementations is helpful for evaluating a mapping decision with tool assistance. Using FFT as an example, this paper introduces a general method to estimate the BER variations due to the finite word length (FWL) effects in implementations by modeling the error as a noise. Quantitatively, the root mean square error due to the FWL effects has been linked to the noise power spectral density (PSD). This leads to the modification of theoretical expressions based on the PSD of the channel noise to estimate the BER. The accuracy of the proposed model is extensively verified using 10 commercial implementations of FFT in 15 different configurations. Additionally, architectures of various FFT implementations have been analyzed and a high-level estimate of latency is provided. Simulation results demonstrate the high accuracy of the proposed models.

Nowadays, the development of embedded system hardware and related system software is mostly carried out using virtual platform environments. The high level of modeling detail (hardware elements are partially modeled in a cycle-accurate fashion) is required for many core design tasks. At the same time, the high computational complexity of virtual platforms caused by the detailed level of simulation hinders their application for modeling large networks of embedded systems. In this paper, we propose the integration of virtual platforms with network simulations, combining the accuracy of virtual platforms with the versatility and scalability of network simulation tools. Forming such a hybrid tool-chain facilitates the detailed analysis of embedded network systems and related important design aspects, such as resource effectiveness, prior to their actual deployment.

Recently, MIMO detectors which are based on Markov Chain Monte Carlo (MCMC) simulation techniques have been proposed as alternatives to, e.g., the well-known sphere detector. In this paper, we present a systematic analysis of the performance of MCMC detectors. We study the impact of several parameters such as the list size and the number of independently running chains. As a performance criterion, our analysis is based on the mutual information over an equivalent modulation channel, rather than on coded bit error rates, because this metric is independent of the outer channel code and provides valuable insights over the whole SNR range of interest. Furthermore, we show that combining the MCMC detector with a hard-output sphere detector removes the error floor at high SNR, which is a well-known problem of the MCMC principle.

In this work, we derive a new upper bound on the achievable rate of stationary Rayleigh flat-fading channels with i.i.d. input symbols. The novelty lies in the fact that this bound is not restricted to peak power constrained input symbols like known bounds, e.g., in [1] or [2]. Therefore, the derived upper bound can also be used to evaluate the achievable rate with i.i.d. proper Gaussian input symbols, which are capacity achieving in the coherent case. The derivation of the upper bound is based on the prediction error variance of the one-step channel predictor.

In this paper, we analyze the error rate degradation caused by the finite-precision extrinsic log-likelihood ratio (LLR), i.e., demapper output, for multiple-input multiple-output (MIMO) bit-interleaved coded modulation with iterative decoding (BICM-ID). A closed-form expression for the probability density function (pdf) of the metric difference with finite precision is derived. This pdf is well-approximated by two approaches, namely the pseudo quantization noise (PQN) model and the pdf tail truncation. Moreover, we interpret such performance degradation as an additional signal-to-noise ratio (SNR) loss. As validated by Monte Carlo simulations, this SNR loss can be directly applied at the first iteration, extending our analysis to non-iterative scenario. This work provides a convenient indicator for deciding the LLR precision in real implementations.

In this paper, the iterative scheduling issue for multiple-input multiple-output (MIMO) systems with turbo codes is addressed based on the informed asynchronous scheduling, initially used for scheduling low-density parity-check (LDPC) decoding. For the iterative MIMO demapping and turbo decoding, the convergence behavior by using the informed asynchronous scheduling is first demonstrated to be similar to the standard sequential scheduling. As the extrinsic log-likelihood ratio (LLR) calculation at both the MIMO demapper and turbo decoder costs high complexity, an informed message update (IMU) rule is further proposed to select only a subset of extrinsic LLRs for updates within each iteration. By avoiding the re-calculations for the extrinsic LLRs with small changes between successive iterations, significant complexity savings are achieved with negligible error rate performance loss.

This paper presents a new approach for intercell interference mitigation with downlink beamforming based on long-term channel state information in a multiuser multicell scenario. In contrast to many previous downlink beamforming approaches, where a group of users is served by one base station (BS), this paper considers an assignment of multiple BSs to a group of users. Inside a user group, unicast transmission to scheduled users or multicast transmission to all users of this group can be applied. A solution based on semidefinite programming for the optimization of the beamforming weights is given and a comparison of the conventional beamforming with a single BS assignment and beamforming with multi-BSs assignment is presented for the two different transmission scenarios. Beamforming with multi-BS assignment outperforms the conventional beamforming with single BS assignment considering fairness among the users, but at the expense of a reduced sum rate in the case of a unicast transmission. An additional improvement of the throughput for users in the cell edge region can be observed.

A common simplification in the treatment of random linear channels is the wide-sense stationary and uncorrelated scattering (WSSUS) assumption. For wireless channels, this assumption is, however, only fulfilled in an approximative sense inside local time-frequency regions. Since algorithms in wireless digital communications often rely on knowledge of second order statistics of the channel, it is important to know the size of local quasi-stationarity regions. Thus, we determine quasi-stationarity regions in distance for an urban macrocell scenario. We observe that, based on the chosen measure and in our specific scenario, the time-frequency properties are dominant compared to the spatial properties in defining the size of quasi-stationarity regions. Furthermore, we find that in some cases the quasi-stationarity regions strongly depend on the mobile terminal orientation.

A common simplification in the treatment of random linear channels is the assumption of stationarity of the channel in time. The wireless channel is, however, known to be inherently non-stationary. We detail a methodology for non-stationarity analysis from an algorithmic perspective. For the determination of local quasi-stationarity regions, we consider a multi-link downlink scenario where multiple base stations use transmit beamforming to concurrently transmit to a single mobile terminal per time slot. We obtain an algorithm-specific measure, i.e., the signal-to-interference-plus-noise ratio (SINR) degradation, with which we evaluate local quasi-stationarity regions. Furthermore, we relate and compare the SINR degradation to the correlation matrix distance (CMD). In an urban macrocell scenario relevant to 3GPP Long Term Evolution (LTE), we find that the resulting local quasi-stationarity distances show the same trends, but that the CMD overestimates the average distances for our system model.

The problem of data detection in MIMO systems is usually studied under the assumption of perfect channel knowledge at the receiver. In practice, however, only a (potentially very poor) estimate of the channel is available. It has been shown that detection algorithms which take the unreliability of the channel estimate into account can significantly outperform their mismatched counterparts (i.e., detectors which use the estimate in lieu of the true channel matrix). In this paper, we extend the Markov Chain Monte Carlo (MCMC) MIMO detector to the case of imperfect channel knowledge. Due to the low complexity of the MCMC algorithm, this technique is also applicable in systems where brute force approaches are computationally infeasible.

The concurrent transmission of cognitive radios (CRs) and primary users (PUs) can achieve high spectral efficiency, provided that the interference power to each PU is limited below a certain threshold. Joint optimization of the precoding and the equalization is widely used to exploit the spatial diversity to mitigate the interference. However, its performance is sensitive to the inevitable imperfect channel state information (CSI). This paper studies the robust transceiver optimization in multiple-input and single-output downlink CR network, aiming at minimizing the worst-case per-user mean square error. The channel uncertainty model is assumed to be ellipsoidal bounded for both channel matrices and short-term channel covariance matrices. Under the uncertainty models for both cases of CSI, we first derive the strict upper bound or equivalent conditions for the constraints, then reformulate the original optimization problem into the semi-definite programming problems which can be efficiently solved. Simulation results demonstrate that the proposed schemes effectively mitigates the performance degradation due to the imperfect CSI. Their robustness with respect to the interference constraint is also validated, which is regarded as the critical part in the design of CR network.

We evaluate the performance of beamforming in the downlink of a Single Frequency Network (SFN), in which common data is transmitted to all participating users simultaneously. The beamforming is jointly optimized for all cells in the network and for all users. The algorithm is based on spatio-temporal correlation knowledge (long term channel state information at the transmitter) and regularly updated, but possibly delayed, SNR information. In a first stage of this algorithm an estimator for the current SNR is built as a function of the beamforming weights. In a second stage of the algorithm, the beamforming weights are optimized in order to maximize the minimum SNR in the system.

This paper introduces a new framework of the multiple-input multiple-output (MIMO) detection in iterative receivers. Unlike the conventional methods processing with symbol lattice, we consider the delta symbol lattice, i.e., the difference between two arbitrary points in the symbol lattice. The inherent flexible, symmetric, and sparse properties of the delta lattice enhance the detection in both complexity and performance aspects. Consequently, we propose a delta-list MIMO (DL-MIMO) detection which separately exploits the channel information and the a priori information so that a soft-input soft-output sphere decoder is dispensable. Simulation results demonstrate this hardware-friendly DL-MIMO detection delivers nearly-optimal performance at affordable cost in a practical scenario.

A well-known problem of OFDM signals is their high peak-to-average power ratio, which can cause the clipping of peaks in the transmitted signal due to the limited linear range of high power amplifiers. Operating the amplifier solely in the linear region, i.e., with a large output back-off, results in an undistorted transmitted signal, but at the expense of a low SNR at the receiver. Driving the amplifier into saturation, on the other hand, maximizes the received SNR, but causes severe nonlinear signal distortions. In this paper we study the resulting tradeoff. We show both theoretically and by simulations that, despite the distortions, it is optimal to operate the amplifier close to saturation. Furthermore, we analytically derive a modification of the Bussgang noise cancellation algorithm which was recently shown in the literature to improve the EXIT characteristic of the algorithm.

Scheduling, mapping and synchronization have an essential impact on the performance of Multi-Processor System-on-Chips (MPSoCs), especially in heterogeneous systems with many cores and small tasks. This paper presents a technique to efficiently accelerate these operations. Key contribution is an Application-Specific Instruction-set Processor (ASIP) called OSIP which is especially tailored to achieve this. In contrast to pure HW solutions, OSIP is programmable and hence features higher flexibility and better scalability. OSIP comes with a compiler and a firmware that ease its usability, and an abstract formal model that allows analytical evaluation and integration into fast system level simulators. Together with OSIP, a thin software layer is proposed that leverages high level multi-task programming by abstracting OSIP's low level details away. In an extensive case study based on a synthetic benchmark and a benchmark from the multimedia domain (H.264), OSIP highlights its potential when compared against a standard RISC and an ARM926-EJS processor.

This paper investigates max-min beamforming for the multicell downlink transmission, where multiple base stations (BSs) cooperatively optimize their transmit beamforming vectors using long-term channel statistics. Based on Lagrangian duality, we reformulate the original problem into a dual uplink problem, which is expected to achieve the same optimal signal to interference plus noise ratio (SINR) as the primal downlink problem. The normalized dual uplink beamformer is the dominant eigenvector of a generalized eigenvalue decomposition (GEVD) problem, and the dual uplink transmit power can be solved iteratively. According to the duality theory, we develop an iterative algorithm and compare it with the beamformer-power iterative algorithm extended from. Simulation results verify the computational efficiency of the proposed algorithm.

Using the Schnorr-Euchner (SE) order for soft-input sphere decoders is inefficient for implementation, because it requires exhaustive calculation and sorting of partial metrics of all constellation points. Instead, low-complexity methods can be applied by separating the partial metric into channel information and a priori information and solely enumerating based on one of them. With such an orthogonalization, this paper presents an algorithm that effectively combines these two enumerations to deliver an order close to the SE one. Mathematical analyses and simulation results demonstrate that this is the first algorithm allowing for a low-complexity implementation with optimal error rate performance for any number of iterations.

Library based waveform (WF) development approaches have the potential to address one of the key challenges in software defined radio technology, developing portable and at the same time implementation-efficient WFs. The term WF, in this paper, represents a complete wireless standard with several modes. Upon standardizing the library and the interfaces of its components, different vendors can provide Flavors, which are efficient implementations, for some/all components of a WF as a board-support-package. Flavors might provide different trade-offs with respect to key performance related properties like bit error rate, throughput, latency, area, etc. This paper analyzes such a scenario by using FFT as an example. We use 10 Flavors of FFT from 2 vendors for 3 processing elements to analyze the influence of configuration parameters like input data-width, scaling, etc. on the performance properties. Analysis has been performed by doing two tests: using a simple OFDM transceiver system, calculating root mean square error. Based on our analysis, we have identified the main parameters that influence the properties. Our investigations stress the need for modeling the differences in performance on key properties in terms of the influencing parameters. Such a model can assist in selecting a set of appropriate Flavors for implementing a WF and enable tool assisted WF-development. Furthermore, it is evident from our investigations that Flavors exhibit trade-offs in properties and pose tough constraints in several aspects.

This paper considers downlink transmit beamforming for a unicast transmission to a multitude of users with the goal of a joint optimization of the beamforming weights from multitude of basestations. In wireless systems, bandwidth is a limited resource. Therefore in this paper, a frequency reuse-1 is applied at the expense of intercell interference. The optimization of the beamforming weights is done with semideflnite programming with the knowledge of long term channel state information (CSI). This paper presents a fair beamforming technique that results in a very low signal to interference and noise rate (SINR) feedback rate. An improvement of the throughput for users in the cell edge region with a constrained transmit power is achieved.

We evaluate the benefit of beamforming for broadcast/multicast transmission using single frequency networks (SFNs), where the beamforming weights are jointly optimized for the base stations participating in the SFN transmission. The aim is to reduce the total transmission power under the constraint of the provision of a certain mean SNR to all users. In order to keep the number of base stations to which a user is connected low, we apply a sensitivity analysis to the optimization problem and identify the users that should connect to further base stations to lower the required transmission power most effectively.

In FDD systems, uplink spatio-temporal correlation knowledge can be obtained via uplink measurements and time- averaging. Many algorithms however require the knowledge of the downlink correlation, such as transmit beamforming in the case of spatial correlation and user SNR prediction algorithms in the case of temporal correlation. This paper shows a way to convert the uplink spatio-temporal correlation to its downlink counterpart using spline interpolation and two dimensional phase unwrapping techniques. Furthermore, applications are shown which highlight the potential benefit of the proposed algorithm.

This paper proposes a new concept of multiple-input multiple-output (MIMO) detection, aiming at minimizing the average computational cost. The detection methods, according to the estimated channel state information, are adapted to deliver just acceptable error rate. Performance of two popular MIMO detectors is analyzed. Based on these analyses, a channel adaptive MIMO (CA-MIMO) receiver with a novel method- selection strategy is investigated. Simulation results demonstrate that the proposed CA-MIMO detector, operating at as low SNR as the sphere search does, achieves huge average complexity saving.

In FDD systems, uplink spatio-temporal correlation knowledge can be obtained via uplink measurements and time-averaging. Many algorithms however require the knowledge of the downlink correlation, such as base-station transmit beam-forming in the case of spatial correlation and user SNR prediction algorithms in the case of temporal correlation. This paper presents two possible algorithms for the conversion of the uplink spatio-temporal correlation to its downlink counterpart and compares their performance in terms of the link-level conversion error.

Retargetable C compilers are currently widely used to quickly obtain compiler support for new embedded processors and to perform early processor architecture exploration. A partially inherent problem of the retargetable compilation approach, though, is the limited code quality as compared to hand-written compilers or assembly code due to the lack of dedicated optimizations techniques. This problem can be circumvented by designing flexible, retargetable code optimization techniques that apply to a certain range of target architectures. This article focuses on target machines with SIMD instruction support, a common feature in embedded processors for multimedia applications. However, SIMD optimization is known to be a difficult task since SIMD architectures are largely nonuniform, support only a limited set of data types and impose several memory alignment constraints. Additionally, such techniques require complicated loop transformations, which are tailored to the SIMD architecture in order to exhibit the necessary amount of parallelism in the code. Thus, integrating the SIMD optimization and the required loop transformations together in a single retargeting formalism is an ambitious challenge. In this article, we present an efficient and quickly retargetable SIMD code optimization framework that is integrated into an industrial retargetable C compiler. Experimental results for different processors demonstrate that the proposed technique applies to real-life target machines and that it produces code quality improvements close to the theoretical limit.

In the past few years, MPSoC has become the most popular solution for embedded computing. However, the challenge of programming MPSoCs also comes as the biggest side-effect of the solution. Especially, when designers have to face the legacy C code accumulated through the years, the tool support is mostly unsatisfactory. In this paper, we propose an integrated framework, MAPS, which aims at parallelizing C applications for MPSoC platforms. It extracts coarsegrained parallelism on a novel granularity level. A set of tools have been developed for the framework. We will introduce the major components and their functionalities. Two case studies will be given, which demonstrate the use of MAPS on two different kinds of applications. In both cases the proposed framework helps the programmer to extract parallelism efficiently.

With the growing number of programmable processing elements in today's Multi Processor System-on-Chip (MPSoC) designs, the synergy required for the development of the hardware architecture and the software running on them is also increasing. In MPSoC development environment, changes in the hardware architecture can bring in extensive re-partitioning or re-parallelization of the software architecture. Fast and accurate functional simulation and performance estimation techniques are needed to cope with this co-design problem at the early phases of MPSoC design space exploration. The current paper addresses this issue by introducing a framework which combines hybrid simulation, cache simulation and online trace-driven replay techniques to accurately predict performance of programmable elements in an MPSoC environment. The resulting simulation technique can easily cope with the continuous re-organizations of software architectures during an Instruction Set Simulator (ISS) based design process. Experimental results show that this framework can improve system simulation speed by 3-5× on average while achieving accuracy closely comparable to traditional ISSes.

The increasing complexity of today's multimedia and wireless applications is motivating the system designers to innovate continuously. With the challenge to keep various performance metrics in a tight balance while designing a complex system, an entire range of components are now being offered as choices for system building blocks. Coarse-Grained Re-configurable Architecture (CGRA), a strongly emerging class, is currently receiving due attention for offering excellent performance as well as flexibility post fabrication. Compared to the programmable and flexible microprocessors these architectures are shown to yield stronger performance, especially in case of regular and data-driven applications. A variety of system designs are proposed of late, with CGRA as one of the key building blocks. Most of the research initiatives taken in this area have resorted to a template-based approach, where the structure of the re-configurable architecture is partially fixed with several tunable parameters. In this paper, we present a language-driven modelling and exploration framework for CGRAs. In the domain of CGRAs, this framework attempts to bring modelling ease, genericity, early exploration and path to implementation together. The modelling formalism proposed in this paper as well as the exploration capabilities are demonstrated via experiments with several algorithmic kernels.

Retargetable C compilers are key components of today's embedded processor design platforms for quickly obtaining compiler support and performing early processor architecture exploration. The inherent problem of the retargetable compilation approach, though, is the well known trade-off between the compiler's flexibility and the quality of generated code. However, it can be circumvented by designing flexible, configurable code optimization techniques applicable to a certain range of target architectures. This paper focuses on target machines with predicated execution support which is wide-spread in deeply pipelined and highly parallel embedded processors used in next generation high-end video, multimedia and wireless devices. We present an efficient and quickly retargetable code optimization technique for predicated execution that is integrated into an industrial retargetable C compiler. Experimental results for several embedded processors demonstrate that the proposed technique is applicable to real-life target machines and that it produces significant code quality improvements for control intensive applications.

Provides an abstract of the tutorial presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings.

In this paper, we consider data-aided carrier frequency estimation for burst mode transmission in low signal-to-noise ratio (SNR) environments. It is well known from literature that it is advantageous for the accuracy of data-aided carrier frequency estimation to choose separate packets of pilot symbols as pilot constellation. We here introduce a new concept to treat such pilot symbol constellations. This concept lowers the SNR threshold for considered frequency estimator and, therefore, allows for accurate frequency recovery at low SNR. Furthermore, it is demonstrated that the approach improves the accuracy of carrier frequency estimation also in the presence of fading.

For modern wideband transmission systems narrowband interference and their identification becomes an important issue especially for weak interferers. This paper theoretically derives an interference detection scheme from EM theory in conjunction with a MAP channel estimation. The approach is related to a previously introduced heuristic scheme [1] and does not require mute periods or carriers, but works on a known burst preamble. Beyond the derivation of the detector-estimator, this work analytically evaluate the estimator variance, showing the value of the scheme.

In this paper, we derive the asymptotic bit error rate (BER) for multiple-input multiple-output bit-interleaved coded modulation (MIMO-BICM) with linear zero-forcing (ZF) receivers for a temporally correlated flat Rayleigh fading channel. Pilot symbol assisted modulation (PSAM) in combination with linear minimum mean-squared error (LMMSE) channel estimation is considered. We also demonstrate that the deterioration due to imperfect channel state information (CSI) can be represented by a signal-to-noise ratio (SNR) degradation.

We consider a stationary Rayleigh flat-fading channel with temporal correlation and a compactly supported power spectral density of the channel fading process. We assume that the channel state is unknown to both transmitter and receiver, while the law of the channel is presumed to be known to the receiver. Given a set of fixed signaling sequences, the optimum input distribution, with respect to the achievable rate, has the property of a constant Kullback-Leibler distance between the output distribution and a mixture of the output distributions conditioned on the different input sequences. Based on this, we determine the set of optimum input distributions for PSK signaling. In addition, we identify the special case of transmitting one pilot symbol to acquire a phase reference as being included in the set of optimum input distributions. We derive an integral expression for the capacity constrained to PSK signaling depending on the autocorrelation of the channel and the SNR. Evaluation of the asymptotic high SNR behavior shows a loss in the constrained capacity with respect to the case of perfect channel knowledge corresponding to at least one signaling dimension, i.e., the information transmitted by one symbol.

In this paper, we investigate turbo-coded transmission over a temporally correlated flat Rayleigh fading channel. Conventionally, channel estimation is performed prior to decoding and is solely based on periodically inserted pilot symbols. We here consider the case that the pilot spacing is not small enough to satisfy the Nyquist criterion for the bandlimited channel process. It is demonstrated that iterative code-aided channel estimation can then significantly improve the bit error rate (BER). Furthermore, we show that the convergence speed of the iterative channel estimation can be significantly accelerated without additional computational power by just carefully choosing the mapping strategy of systematic bits to data symbols.

We examine the application of beamforming in a single frequency network (SFN) for the provision of multicast services. A single frequency network is characterized by the simultaneous transmission of the same signal from multiple base stations. Since each user receives the signal from several base stations, the beamforming weights for many different base stations need to be jointly optimized for the transmission in order to give optimal results. The determination of the beamforming weights that maximize the minimum SNR is a nonconvex problem. A constraint relaxation however yields a convex program, which can be solved with fast algorithms at only a slight loss of performance. Furthermore, this convex formulation of the problem gives solutions that perform significantly better than omnidirectional transmission.

Modern application-specific instruction-set processors (ASIPs) face the daunting task of delivering high performance for a wide range of applications. For enhancing the performance, architectural features, for example, pipelining, VLIW, are often employed in ASIPs, leading to high design complexity. Integrated ASIP design environments, like template-based approaches and language-driven approaches, provide an answer to this growing design complexity. At the same time, increasing hardware design costs have motivated the processor designers to introduce high flexibility in the processor. Flexibility, in its most effective form, can be introduced to the ASIP by coupling a reconfigurable unit to the base processor. Because of its obvious benefits, several reconfigurable ASIPs (rASIPs) have been designed for years. This design paradigm gained momentum with the advent of coarse-grained FPGAs, where the lack of domain-specific performance common in general-purpose FPGAs are largely overcome by choosing application-dependent basic functional units. These rASIP designs lack a generic flow from high-level specification, resulting in intuitive design decisions and hard-to-retarget processor design tools. Although partial, template-based approaches for rASIP design is existent, a clear design methodology especially for the prefabrication architecture exploration is not present. In order to address this issue, a high-level specification and design methodology for partially reconfigurable VLIW processors is proposed in this article. To show the benefit of this approach, a commercial VLIW processor is used as the base architecture and two domains of applications are studied for potential performance gain.

During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable application-specific instruction set processors (rASIPs) which combine a programmable base processor with a reconfigurable fabric. Although such processors promise to deliver excellent balance between performance and flexibility, their design remains a challenging task. The key to the successful design of a rASIP is combined architecture exploration of all the three major components: the programmable core, the reconfigurable fabric, and the interfaces between these two. This work presents a design flow that supports fast architecture exploration for rASIPs. The design flow is centered around a unified description of an entire rASIP in an architecture description language (ADL). This ADL description facilitates consistent modeling and exploration of all three components of a rASIP through automatic generation of the software tools (compiler tool chain and instruction set simulator) and the RTL hardware model. The generated software tools and the RTL model can be used either for final implementation of the rASIP or can serve as a preoptimized starting point for implementation that can be hand optimized afterward. The design flow is further enhanced by a number of automatic application analysis tools, including a fine-grained application profiler, an instruction set extension (ISE) generator, and a data path mapper for coarse grained reconfigurable architectures (CGRAs). We present some case studies on embedded benchmarks to show how the design space exploration process helps to efficiently design an application domain specific rASIP.

In this correspondence, we analytically derive the bit error rate (BER) for bit-interleaved coded modulation (BICM) under the assumption of a temporally correlated flat Rayleigh fading channel. We assume the channel state information (CSI) to be unknown at receiver side and consider a linear minimum mean-squared error (LMMSE) channel estimator that relies on periodically inserted pilot symbols. We give asymptotic results for both non-iterative BICM and BICM with iterative decoding (BICM-ID). Furthermore, we show that the interpretation of the channel estimation error as an SNR degradation holds true in these cases.

Instruction Set Simulators (ISSes) are important tools for cross-platform software development. The simulation speed is a major concern and many approaches have been proposed to improve the performance of ISSes. A prevalent technique is compiled simulation, which translates target programs into host instructions. But orders of magnitude of speed deterioration is inevitable since the difference between target and host Instruction Set Architectures (ISAs) can be large. An alternative is to emulate the program without sticking to binary compatibility. The performance problem is solved by using native execution. However, these emulators either require a special programming language, or a given Application Programming Interface (API). Last but not least, it is not trivial to integrate an emulator into a system simulator (which provides devices, external memory, etc., that the embedded programmers do care). In this paper, we propose a fast and generic hybrid simulation approach using virtualization technique to accelerate simulation and simulator-based debugging of C programs. A novel virtual coprocessor (VCP) is introduced as a processing element which executes C functions at high speed. This approach is C89 compliant and compatible with third party libraries and platform dependent code. It is also retargetable and can be integrated with existing ISSes. Two different ISAs are supported at present: MIPS and mAgic DSP. The average execution speed of the coprocessor is about 100 million simulated instructions per second.

In today's embedded processors, performance and flexibility have become the two key attributes. These attributes are often conflicting. The best performance is obtained from custom designed integrated circuits. In contrast, the maximum flexibility is delivered by a general purpose processor. Among the architecture types emerged over the past years to strike an optimum balance between these two attributes, two are prominent. The first ones are field programmable gate array (FPGA)-based architectures and the second ones are application-specific instruction-set processors (ASIPs). Depending on the type of application (i.e. stream-like or control-dominated) either one of the above mentioned architecture types is able to deliver high performance or flexibility or both. Consequently, a new design approach with partial re-configurability on the application-specific processor is attracting strong research interest. We call this architecture re-configurable ASIP (rASIP). Currently, the lack of a high-level abstraction of the rASIP limits the designer from trying out various design alternatives because of long and tedious exploration cycles. To address this issue, in this paper, a high-level specification for re-configurable processors is proposed. Furthermore, a seamless design space exploration methodology using this specification is proposed

The high peak-to-average power ratio is a major drawback of OFDM systems. Many PAPR reduction techniques have been proposed in the literature, among them a method that uses a subset of tones that do not carry any data, but are modulated such that the PAPR of the resulting time domain signal is minimized. Another problem of OFDM systems is the high out-of-band power caused by the sidelobes of the modulated tones. The OBP can be reduced by modulating reserved tones at the edges of the occupied spectrum so that the sidelobes of the data carriers are reduced. In this paper, we propose to consider both optimization problems jointly. This way, the amount of PAPR and OBP reduction can be significantly enhanced in comparison to a system that performs two separate optimization steps. Furthermore, the joint reduction algorithm offers more flexibility, because the relative weighting of the two optimization criteria can easily be changed, resulting in a smooth trade-off curve.

The conflicting requirements of performance and flexibility in today 's embedded system market are forcing system designers to use more and more of the so called configurable or customizable processor cores. Such processors tend to meet the demanding performance constraints by accommodating application specific instruction set extensions (ISEs) which have, naturally, become a vital component of current processor customization flows. One major bottleneck in maximizing ISE performance is the limitation on the data-bandwidth between the general purpose register (GPR) file and the ISEs. For improved performance, it is desirable to have a large data-bandwidth from the GPRs to ISEs. However, the tight area constraints of modern embedded processors often restrict the GPR I/O of ISEs to save port area of the register files. This paper presents a novel approach to increase the GPR I/O of ISEs without significantly increasing the size of the GPR files. This is achieved by applying the concept of register clustering, common in many VLIW architectures, to single-issue processors with high performance ISEs. Such clustering often causes extra register moves in compiled code. This work also presents an algorithm to minimize such register moves. The benchmark results presented in this paper show that our solution can significantly reduce the area overhead of many-port GPR files without sacrificing the performance improvements through ISEs.

When realizing carrier frequency offset estimation at low signal-to-noise ratios, a typical feed-forward synchronization unit solely relies on known pilot symbols. The importance of the position of these pilot symbols within the burst has been elaborated on in the literature. In this paper, we discuss the importance of the pilot symbol constellation for iterative code-aided synchronization. Furthermore, we investigate the transmission order of data symbols for a turbo coded system with code-aided synchronization.

In this paper, opportunistic beamforming for HSDPA is considered. Opportunistic beamforming can jointly increase the system throughput and the quality of service in multiuser communication systems with proportional-fair scheduling, since with this beamforming scheme a user experiences more fading peaks in a given period of time. However, the existence of an SINR feedback delay from the user to the base station degrades the performance in such a system rapidly due to outdated and thus mismatched SINR information. Here, the prediction of the SINR in the base station is proposed with a predictor structure that is matched to the beamforming process.

Opportunistic beamforming (OBF) is a technique to jointly increase the throughput and quality of service (QoS) in a multiuser system with fair and channel-aware scheduling. With this technique, the channel dynamics are influenced such that fading peaks occur more often within a given period of time. Channel-aware scheduling requires reliable SNR information in the base station that is obtained via feedback information from the users. Since this feedback is not instantaneous, the problem caused by a feedback delay are exacerbated by OBF because of higher channel dynamics. In this paper, a SNR predictor is derived for OBF that is matched to the beamforming process.

Application-Specific Instruction-Set Processors (ASIPs) are becoming increasingly popular in the world of customized, application-driven System-on-Chip (SoC) designs. Efficient ASIP design requires an iterative architecture exploration loop---gradual refinement of the processor architecture starting from an initial template. To accomplish this task, design automation tools are used to detect bottlenecks in embedded applications, to implement application-specific processor instructions, and to automatically generate the required software tools (such as instruction-set simulator, C-compiler, assembler, and profiler), as well as to synthesize the hardware. This paper describes an architecture exploration loop for an ASIP coprocessor that implements common encryption functionality used in symmetric block cipher algorithms for internet protocol security (IPSec). The coprocessor is accessed via shared memory and, as a consequence, our approach is easily adaptable to arbitrary main processor architectures. This paper presents the extended version of our case study that has been already published on the SCOPES conference in 2004. In both papers, a MIPS architecture is used as the main processor and Blowfish as encryption algorithm.

Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power optimization techniques are strongly applied during the development of modern application specific instruction set processors (ASIPs). Electronic system level design tools based on architecture description languages (ADL) offer a significant reduction in design time and effort by automatically generating the software tool-suite as well as the register transfer level (RTL) description of the processor. In this paper, the automation of power optimization in ADL-based RTL generation is addressed. Operand isolation is a well-known power optimization technique applicable at all stages of processor development. With increasing design complexity several efforts have been undertaken to automate operand isolation. In pipelined datapaths, where isolating signals are often implicitly available, the traditional RTL-based approach introduces unnecessary overhead. We propose an approach which extracts high-level structural information from the ADL representation and systematically uses the available control signals. Our experiments with state-of-the-art embedded processors show a significant power reduction (improvement in power efficiency)

The increasing demands of high-performance in embedded applications under shortening time-to-market has prompted system architects in recent time to opt for multi-processor systems-on-chip (MP-SoCs) employing several programmable devices. The programmable cores provide a high amount of flexibility and reusability, and can be optimized to the requirements of the application to deliver high-performance as well. Since application software forms the basis of such designs, the need to tune the underlying SoC architecture for extracting maximum performance from the software code has become imperative. In this paper, we propose a framework that enables software development, verification and evaluation from the very beginning of MP-SoC design cycle. Unlike traditional SoC design flows where software design starts only after the initial SoC architecture is ready, our framework allows a co-development of the hardware and the software components in a tightly coupled loop where the hardware can be refined by considering the requirements of the software in a stepwise manner. The key element of this framework is the integration of a fine-grained software instrumentation tool into a system-level-design (SLD) environment to obtain accurate software performance and memory access statistics. The accuracy of such statistics is comparable to that obtained through instruction set simulation (ISS), while the execution speed of the instrumented software is almost an order of magnitude faster than ISS. Such a combined design approach assists system architects to optimize both the hardware and the software through fast exploration cycles, and can result in far shorter design cycles and high productivity. We demonstrate the generality and the efficiency of our methodology with two case studies selected from two most prominent and computationally intensive embedded application domains.

Sophisticated C compiler support for network processors (NPUs) is required to improve their usability and consequently, their acceptance in system design. Nonetheless, high-level code compilation always introduces overhead, regarding code size and performance compared to handwritten assembly code. This overhead result partially from high-level function calls that usually introduce memory accesses in order to save and reload registers contents. A key feature of many NPU architectures is hardware multithreading support, in the form of separate register files, for fast context switching between different application tasks. In this paper, a new NPU code optimization technique to use such HW contexts is presented that minimizes the overhead for saving and reloading register contents for function calls via the runtime stack. The feasibility and the performance gain of this technique are demonstrated for the Infineon Technologies PP32 NPU architecture and typical network application kernels

Orthogonal frequency division multiplexing (OFDM) is a data transmission technique which is used in wired and wireless digital communication systems. In this technique, fast Fourier transformation (FFT) and inverse FFT (IFFT) are kernel processing blocks in an OFDM system, and are used for data (de)modulation. OFDM systems are increasingly required to be flexible to accommodate different standards and operation modes, in addition to being energy-efficient. A trade-off between these two conflicting requirements can be achieved by employing application-specific instruction-set processors (ASIPs). In this paper, two ASIP design concepts for the cached FFT algorithm (CFFT) are presented. A reduction in energy dissipation of up to 25% is achieved compared to an ASIP for the widely used Cooley-Tukey FFT algorithm, which was designed by using the same design methodology and technology. Further, a modified CFFT algorithm which enables a better cache utilization is presented. This modification reduces the energy dissipation by up to 10% compared to the original CFFT implementation

In this paper we derive an enhanced power control algorithm, fitting into the up/down control scheme, as it is considered in the frequency division duplex (FDD) mode of the current 3GPP standard. Analysis of the classical up/down power control scheme unveils, that with increasing velocities the power control performance degrades, as the fixed step size power control is not able to track the channel fading properly. For the uplink we derive a nonlinear control algorithm generating the up/down power control commands accounting for the future of the channel fading process. Simulations show that this algorithm in combination with perfect future channel state information can partially mitigate the drawbacks of a fixed step-size up/down power control. A prerequisite for predictive power control is the acquisition of the future channel state information. In this paper we deduce a robust and adaptive structure for the prediction of the channel fading process in the context of a power controlled code division multiple access (CDMA) system based on least mean square (LMS) adaptation. Link level simulations show a signal to noise and interference ratio (SINR) gain in terms of the block error rate, enabling a decrease of the target SINR and thus leading to an enhanced spectral efficiency.

Fast Fourier transformation (FFT) and its inverse (IFFT) are used in orthogonal frequency division multiplexing (OFDM) systems for data (de)modulation. The transformations are the kernel tasks in an OFDM implementation, and are the most processing-intensive ones. Recent trends in the electronic consumer market require OFDM implementations to be flexible, making a trade-off between area, energy-efficiency, flexibility and timing a necessity. This has spurred the development of application-specific instruction-set processors (ASIPs) for FFT processing. Parallelization is an architectural parameter that significantly influence design goals. This paper presents an analysis of the efficiency of parallelization techniques for an FFT-ASIP. It is shown that existing techniques are inefficient for high throughput applications such as ultra wideband (UWB), because of memory bottlenecks. Therefore, an interleaved execution technique which exploits temporal parallelism is proposed. With this technique, it is possible to meet the throughput requirement of UWB (409.6 Msamples/s) with only 4 non-trivial butterfly units for an ASIP that runs at 400MHz

The achievable data rate of an OFDM system using data-aided channel estimation in the high bandwidth regime is evaluated under the assumption of a frequency selective, continuously fading channel. As previous results propose, the achievable data rate depends on the LMMSE channel estimate, for which a convenient representation is introduced here. The mean square estimation error is derived from this representation, allowing for an analysis with respect to the optimum amount and distribution of the pilot symbols in the wideband regime. The results on the data rate show good accordance to previous results based on non-data aided channel prediction especially in the interesting bandwidth range

The growth of the Internet in the last decade has made current networking applications immensely complex. Systems running such applications need special architectural support to meet the tight constraints of power and performance. This paper presents a case study of architecture exploration and optimization of an application specific instruction set processor (ASIP) for networking applications. The case study particularly focuses on the effects of instruction set customization for applications from different layers of the protocol stack. Using a state-of-the-art VLIW processor as the starting template, and architecture description language (ADL) based architecture exploration tools, this case study suggests possible instruction set and architectural modifications that can speed-up some networking applications up to 6.8 times. Moreover, this paper also shows that there exist very few similarities between diverse networking applications. Our results suggest that, it is extremely difficult to have a common set of architectural features for efficient network protocol processing and, ASIPs with specialized instruction sets can become viable solutions for such an application domain.

Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design space exploration is well supported by numerous tools providing high flexibility and quality, the methodology of automated implementation is limited to simple transformations. Assuming fixed architectural templates, information given in the ADL is directly mapped to a hardware description on Register Transfer Level (RTL). Gate-Level synthesis tools are not able to perform potential optimizations, as the computational complexity grows exponential with the size of the architecture. Information such as exclusiveness, parallelism or boolean relations are spread over multiple modules and therefore hard to determine. In this paper, we present an ASIP synthesis approach from architecture description languages, based on an Intermediate Representation (IR). The IR is the key technology to provide new language-independent high-level optimizations and to realize different hardware description language backends. The feasibility of our approach is proven in a case-study.

Current Application Specific Instruction set Processor (ASIP) design methodologies are mostly based on iterative architecture exploration that uses Architecture Description Languages (ADLs) and retargetable software development tools. However, for improved design efficiency, additional pre-architecture exploration tools are required to help narrow-down the huge design space and making coarsegrained Instruction Set Architecture (ISA) decisions before detailed ADL modeling. Extensive application code profiling is the key in such early design stages. Based on a novel code instrumentation technology, we present a microprofiling approach that fills the current gap between source-level and instruction-level profilers and combines their advantages w.r.t. speed and accuracy. We show how the microprofiler is embedded into an advanced ASIP design flow and justify its use in a case study to design an MP3 decoder ASIP.

Efficient architecture exploration and design of application specific instruction-set processors (ASIPs) requires retargetable software development tools, in particular C compilers that can be quickly adapted to new architectures. A widespread approach is to model the target architecture in a dedicated architecture description language (ADL) and to generate the tools automatically from the ADL specification. For C compiler generation, however, most existing systems are limited either by the manual retargeting effort or by redundancies in the ADL models that lead to potential inconsistencies. We present a new approach to retargetable compilation, based on the LISA 2.0 ADL with instruction semantics, that minimizes redundancies while simultaneously achieving a high degree of automation. The key of our approach is to generate the mapping rules needed in the compiler's code selector from the instruction semantics information. We describe the required analysis and generation techniques, and present experimental results for several embedded processors.

Heterogeneous multi-processor SoC (MP-SoC) platforms bear the potential to optimize conflicting performance, flexibility and energy efficiency constraints as imposed by demanding signal processing and networking applications. However, in order to take advantage of the available processing and communication resources, an optimal mapping of the application tasks on to the platform resources is of crucial importance. We propose a SystemC-based simulation framework, which enables the quantitative evaluation of application-to-platform mappings by means of an executable performance model. The key element of our approach is a configurable event-driven virtual processing unit to capture the timing behavior of multi-processor/multi-threaded MP-SoC platforms. The framework features an XML-based declarative construction mechanism of the performance model to accelerate navigation significantly in large design spaces. The capabilities of the proposed framework in terms of design space exploration is presented by a case study of a commercially available MP-SoC platform for networking applications. Focussing on the application to architecture mapping, our introduced framework highlights the potential for optimization of an efficient design space exploration environment.

Phase locked loops (PLL) for RF carrier synthesis often employ oscillators that insert a considerable amount of time varying phase noise into the received signal. That noise must then be removed in the digital baseband receiver. This phase noise is an indivisible superposition of noise components from receiver and transmitter. Regarding systems with multiple transmit and receive antennas (MIMO) and if multiple PLL for carrier synthesis are used each of the superposed phase noise processes per transmit and receive antenna pair can be measured at the receiver. This paper provides a new scheme for high SNR scenarios that exploits spatial correlation between these overlaying phase noise processes at the receiver in order to improve estimation and compensation of the phase noise. Therefore the Wiener filter approach is applied.

Retargetable C compilers are key tools for efficient architecture exploration for embedded processors. In this paper we describe a novel approach to retargetable compilation based on LISA, an industrial processor modeling language for efficient ASIP design. In order to circumvent the well-known trade-off between flexibility and code quality in retargetable compilation, we propose a user-guided, semiautomatic methodology that in turn builds on a powerful existing C compiler design platform. Our approach allows to include generated C compilers into the ASIP architecture exploration loop at an early stage, thereby allowing for a more efficient design process and avoiding application/architecture mismatches. We present the corresponding methodology and tool suite and provide experimental data for two real-life embedded processors that prove the feasibility of the approach.

Architecture description languages are widely used to perform architecture exploration for application-driven designs, whereas the RT-level is the commonly accepted level for hardware implementation. For this reason, design parameters such as timing, area or power consumption cannot be taken into consideration accurately during design space exploration. Design automation tools currently used to bridge this gap are either limited in the flexibility provided or only generate fragments of the architecture. This paper presents a synthesis tool which preserves the full flexibility of the architecture description language LISA, while being able to generate the complete architecture on RT-level using systemC. This paper also presents two real world architecture case studies to prove the feasibility of our approach.

Current and future SoC designs will contain an increasing number of heterogeneous programmable units combined with a complex communication architecture to meet flexibility, performance and cost constraints. Designing such a heterogenous MP-SoC architecture bears enormous potential for optimization, but requires a system-level design environment and methodology to evaluate architectural alternatives. This paper proposes a methodology to jointly design and optimize the processor architecture together with the on-chip communication based on the LISA Processor Design Platform in combination with systemC transaction level models. The proposed methodology advocates a successive refinement flow of the system-level models of both the processor cores and the communication architecture. This allows design decisions based on the best modeling efficiency, accuracy and simulation performance possible on the respective abstraction level. The effectiveness of our approach is demonstrated by the exemplary design of a dual-processor JPEG decoding system.

Two different power-scaled noncoherent detection schemes are analyzed and compared in terms of detection probability and mean detection time in the uplink of a wideband CDMA system, where the mobile terminal transmits a pilot signal in the form of bursts of modulated chips, which are transmitted periodically and separated by long silent intervals. Both detection schemes employ temporal noncoherent averaging but differ in the way of spatial processing. One of the schemes, which is well suited for spatially uncorrelated scenarios, employs spatial noncoherent averaging, whereas the other scheme, better suited for scenarios with a distinct spatial structure, employs fixed beamforming. The performance analysis is carried out for spatially correlated frequency-selective fading channels taking channel dynamics and initial frequency offsets into account. With the presented analysis it is possible to investigate the effects of spatial correlation on the detection performance and to examine the improvement of using multiple antenna elements at the base station depending on the respective detection scheme.

We examine the technique of random beamforming to exploit multiuser diversity in the downlink of a wireless cellular communication system with an antenna array at the basestation. In random beamforming systems, the scalar signal is multiplied by a weight vector and the resulting signal vector is transmitted by the antenna array. By varying the weight vector in time, one can increase the dynamic of the effective channel resulting in faster fading and a larger variance of the effective channel. This can be exploited by a scheduler at the basestation which selects users for transmission that momentarily have a good channel. Our work focusses on the generation of the weight vectors for a uniform linear array in the basestation. We especially consider correlation between the antenna elements, but assume that the correlation matrices for the different users are not known to the basestation. Three random beamforming approaches are compared with the simplest possible case of using equal weights, where the weight vector is a constant which serves only to normalize the radiated power. We derive the mean of the received power for the different beamforming techniques and confirm our results by Monte Carlo simulations, where we evaluate the mean power of the actually scheduled user, if a proportional fair scheduling algorithm is used. One important result is the good performance of the rotating beam approach even in a not fully correlated environment.

An optimal phase synchronization and automatic gain control (AGC) scheme for coherent reception of linearly modulated signals on frequency-flat mobile fading channels is presented. The channel model and receiver performance are described. It is shown that using the technique allows the irreducible error floors (due to random FM) known from the noncoherent methods to be practically eliminated. Depending on the fastness of the fading, large power gains over the noncoherent methods are achieved. Unfavorable analog signal processing and/or the high bandwidth inefficiency of the FDM-pilot coherent methods are also avoided.>

An efficient method to generate exactly WMC-distributed random numbers on a digital computer is presented. The generation is based on the acceptance-rejection method. The WMC distribution is used to model the statistical behavior of avalanche photodiodes (APD), for example, in the simulation of optical transmission.>

Unified modeling and estimation of the MD (multiplicative distortion) in finite-alphabet digital communication systems is presented. A simple form of MD is the carrier phase exp(j theta ), which has to be estimated and compensated for in a coherent receiver. A more general case with fading must, however, allow for amplitude as well as phase variations of the MD. The authors assume a state-variable model for the MD and generally obtain a nonlinear estimation problem with additional randomly varying system parameters such as received signal power, frequency offset, and Doppler spread. An extended Kalman filter is then applied as a near-optimal solution to the adaptive MD and channel parameter estimation problem. Examples are given to show the use and some advantages of this scheme.>

Using the maximum-likelihood approach, algorithms for detection and synchronization are derived that are well suited for VLSI implementation. Special emphasis is placed on an all-digital implementation where carrier and clock synchronization do not require a feedback of signals to the analog part, which simplifies the analog front-end design (mixing oscillator and A/D converter sampling clock run at fixed frequency). An important advantage of the proposed algorithms is that a high clock rate is not required; only two-four times the symbol rate is needed, depending on amplitude quantization. Implementation aspects, e.g. architecture, and quantization, are considered. A prototype is described which was implemented to prove the feasibility of the concept and to evaluate the performance under practical conditions.>

Cycle slips in phase-locked loops are statistical, nonlinear phenomena. This makes a mathematical analysis extremely difficult. As a consequence, the results of such an analysis are not easily accessible to the practicing engineer. It is the purpose of this survey paper to present a self-contained discussion of cycle slips in phase-locked loop avoiding advanced mathematical tools. Based on the results of an extensive experimental study we explain the underlying principle of the complex interaction between nonlinearity and noise. The results are complemented by simple, approximate analysis which agrees well with the experimental findings. In addition, we present a new and complete set of diagrams on cycle slip statistics not presently available in the literature.