Integrated sensing and communication (ISAC) is a key enabling technology for sixth-generation (6G) mobile communication systems, achieving seamless integration of communication and sensing functions. Cooperative sensing, where the transmitter and receiver are not co-located, serves as a key enabler for ISAC, significantly enhancing the sensing performance while reducing the implementation complexity of the receiver. However, practical deployments of cooperative sensing still face numerous challenges, such as synchronization and interference. This paper presents a set of advanced beam management methods specifically designed for the cooperative sensing system, offering a comprehensive framework to address these challenges. Specifically, we first analyze the strong/weak path effect (SWPE), a critical phenomenon caused by diverse target reflectivities and propagation paths, which severely degrades both synchronization accuracy and target detection. To counteract this, we propose an adaptive path power allocation method compatible with both all-digital and hybrid beamforming architectures. This method intelligently allocates power across different paths to mitigate the SWPE, thereby ensuring reliable synchronization via the direct path while enhancing the detectability of weak targets. As a result, the proposed method improves the target detection probability by over 30%. Furthermore, an adaptive interference suppression method is designed to reduce interference while maintaining sensing/communication quality, which obtains the SINR gain of around 5 dB, compared to the traditional full nulling method. Experimental results validate the effectiveness of robust synchronization and our proposed power allocation. This study lays a solid foundation for beamforming optimization in cooperative sensing systems, facilitating high-accuracy sensing and communication in complex environments.

The scarcity of annotated data is an important factor restricting the multi-organ segmentation technology. To address this issue, recent research has introduced prototype-based method into the realm of multi-organ segmentation. However, existing prototype-based method have focused only on specific ranges of local feature information, neglecting the impact of local feature information across different ranges on segmentation results. In this paper, we proposed a multi-organ segmentation model based on multi-granularity prototype learning (MGPL_Net), which can make full use of different local feature information by obtaining multi-granularity prototypes. Firstly, we proposed a multi-granularity prototype extraction and fusion (MGPEF) mechanism to effectively utilize different local feature information of support image. Secondly, we proposed a multi-granularity prototype alignment (MGPA) mechanism to enhance the representation capability of local prototypes at different granularities by establishing information closed-loop between support and query. We conducted experiments on two datasets, validating the effectiveness of this approach. The segmentation accuracy improved by 3.91% on the ABD-MRI dataset and by 7.28% on the ABD-CT dataset.

Over the past two decades, advances in materials science and electronics have greatly supported the progress of the communication industry, and the emergence of new materials has made it possible to design higher performance communication modules. As a potential key technology for future 6G networks, the standardisation and industrialisation of visible light communication (VLC) cannot be separated from the improvement of the communication devices. In this paper, we first analyse and summarise the performance enhancement of new materials and designs of VLC devices. Then the support of improved capabilities of novel VLC devices for 6G new services is prospected. As device performance improves, VLC is expected to support more scenarios in 6G.

It is challenging to automatically explore an unknown 3D environment with a robot only equipped with depth sensors due to the limited field of view. We introduce THP, a tensor field-based framework for efficient environment exploration which can better utilize the encoded depth information through the geometric characteristics of tensor fields. Specifically, a corresponding tensor field is constructed incrementally and guides the robot to formulate optimal global exploration paths and a collision-free local movement strategy. Degenerate points generated during the exploration are adopted as anchors to formulate a hierarchical TSP for global path optimization. This novel strategy can help the robot avoid long-distance round trips more effectively while maintaining scanning completeness. Furthermore, the tensor field also enables a local movement strategy to avoid collision based on particle advection. As a result, the framework can eliminate massive, time-consuming recalculations of local movement paths. We have experimentally evaluate our method with a ground robot in 8 complex indoor scenes. Our method can on average achieve 14% better exploration efficiency and 21% better exploration completeness than state-of-the-art alternatives using LiDAR scans. Moreover, compared to similar methods, our method makes path decisions 39% faster due to our hierarchical exploration strategy.

In this paper, reconfigurable intelligent surface (RIS) is employed in a millimeter wave (mmWave) integrated sensing and communications (ISAC) system. To alleviate the multi-hop attenuation, the semi-self sensing RIS approach is adopted, wherein sensors are configured at the RIS to receive the radar echo signal. Focusing on the estimation accuracy, the Cramér-Rao bound (CRB) for estimating the direction-of-the-angles is derived as the metric for sensing performance. A joint optimization problem on hybrid beamforming and RIS phase shifts is proposed to minimize the CRB, while maintaining satisfactory communication performance evaluated by the achievable data rate. The CRB minimization problem is first transformed as a more tractable form based on Fisher information matrix (FIM). To solve the complex non-convex problem, a double layer loop algorithm is proposed based on penalty concave-convex procedure (penalty-CCCP) and block coordinate descent (BCD) method with two sub-problems. Successive convex approximation (SCA) algorithm and second order cone (SOC) constraints are employed to tackle the non-convexity in the hybrid beamforming optimization. To optimize the unit modulus constrained analog beamforming and phase shifts, manifold optimization (MO) is adopted. Finally, the numerical results verify the effectiveness of the proposed CRB minimization algorithm, and show the performance improvement compared with other baselines. Additionally, the proposed hybrid beamforming algorithm can achieve approximately 96% of the sensing performance exhibited by the full digital approach within only a limited number of radio frequency (RF) chains.

Monocular depth estimation is a challenging problem on which deep neural networks have demonstrated great potential. However, depth maps predicted by existing deep models usually lack fine-grained details due to convolution operations and down-samplings in networks. We find that increasing input resolution is helpful to preserve more local details while the estimation at low resolution is more accurate globally. Therefore, we propose a novel depth map fusion module to combine the advantages of estimations with multi-resolution inputs. Instead of merging the low- and high-resolution estimations equally, we adopt the core idea of Poisson fusion, trying to implant the gradient domain of high-resolution depth into the low-resolution depth. While classic Poisson fusion requires a fusion mask as supervision, we propose a self-supervised framework based on guided image filtering. We demonstrate that this gradient-based composition performs much better at noisy immunity, compared with the state-of-the-art depth map fusion method. Our lightweight depth fusion is one-shot and runs in real-time, making it 80X faster than a state-of-the-art depth fusion method. Quantitative evaluations demonstrate that the proposed method can be integrated into many fully convolutional monocular depth estimation backbones with a significant performance boost, leading to state-of-the-art results of detail enhancement on depth maps. Codes are released at https://github.com/yuinsky/gradient-based-depth-map-fusion.

Recently, the edge-device DNN training has become of high importance, while the computation and access energy consumption of are too large. This paper proposes a CPE (Compress Process Element) with three characteristics. Firstly, CPE has a method of Reordering and Reusing Data (RRD) by controlling the output to reorder data. Secondly, CPE owns a Multi-directional Redundant Skip (MRS) mechanism, which anticipates all zeros and duplicate fields in advance. Thirdly, CPE contains a scheme to transform The Calculation Format (TCF), which transforms the input into another form. Evaluated with 28nm CMOS process, using CPE achieves 2.02 × energy reduction and offer 1.73 × speed up outperforming state-of-the-art trainable processor GANPU.

Coarse-Grained Reconfigurable Architecture (CGRA), especially the one with multiple parallelized Processing Element Arrays (PEA), possesses flexible programmability and high parallel computational efficiency, which relies upon an efficient memory architecture to deliver the corresponding computing power. Multi-PEA oriented CGRA allows for mapping various applications and thus demands a flexible memory to adapt to the ever-changing workloads, whose parallel access also requires an efficient multi-port memory. However, the existing memory designs for CGRA are hard to satisfy those requirements since conventional rigid memories fail to provide the desired flexibility due to fixed structure, and traditional multi-port designs are impractical due to large overhead. Therefore, this paper proposes a hardware/software (HW/SW) hybrid reconfigurable multi-port memory architecture (RMP-MEM) with an instructive analysis for the multi-PEA oriented CGRA. RMP-MEM supports adaptive memory partition and programmer-defined access modes to adapt the different features of memory accesses. Also, RMP-MEM achieves an efficient multi-port implementation by a partially shared mechanism. Furthermore, the microarchitecture of RMP-MEM is optimized multi-directionally, resulting in a significant performance gain. The experimental results indicate that RMP-MEM reduces the parallel access latency by 81.1% and exhibits 28.3% energy efficiency improvement compared to prior designs.

Spatial architecture is a high-performance architecture that uses control flow graphs and data flow graphs as the computational model and producer/consumer models as the execution models. However, existing spatial architectures suffer from control flow handling challenges. Upon categorizing their PE execution models, we find that they lack autonomous, peer-to-peer, and temporally loosely-coupled control flow handling capability. This leads to limited performance in intensive control programs.

Visible light communications (VLC) is considered a potential key technology for 6G. However, the performance of transceiver devices of VLC determines the upper limit of system. InGaN/GaN based light-emitting diodes (LEDs) have widely been used as the transmitter. In this paper, a VLC transceiver system is designed on the basis of InGaN/GaN blue light laser diode (LD). The transmitted signals are designed based on the 5G new radio (NR) physical layer protocol. The experiment verifies the feasibility of 256 quadrature amplitude modulation (QAM) and the blue LD-based VLC system can achieve up to 14Gbit/s system sum rate when adopting 5G NR protocol, which contributes to the application of VLC in 6G systems.

Abstract Building non‐volatile main memory (NVMM) systems requires the memory data to be encrypted to remedy the potential security vulnerability caused by the non‐volatile property of NVMM. Existing solutions still have shortcomings as vulnerability of security, inadequate optimizing of performance, and other limitations hold back their deployment into real systems. This paper proposes an address‐based counter mode encrypted NVMM system. It constructs a stand‐alone memory‐side secure engine to make counter mode encryption and maintains the crucial encryption parameter of counter by adopting the address‐based strategy. Compared with existing techniques, it provides the distinct advantages of: (1) higher assurance of security through encrypting any data at any time; (2) better performance, as nearly all of the encryption/decryption latencies are removed; (3) good feasibility due to the lowest‐level protection, ultra simple structure with low implementation cost, as well as no need for further adjustments, and it can also be made available for a wide range of target platforms; (4) helpful to improve the lifetime of NVMM without side‐effects to wear‐leveling techniques. Performance evaluation shows the overall performance slowdown has an average value of 0.072%, which proves the proposed method is an effectual way to implement data protection for NVMM systems. Copyright © 2014 John Wiley & Sons, Ltd.

Providing resistance against hardware attacks is important to ensure trusted or secure computing. Approach of inter-chip authentication is proposed, which can be applied to detect malicious tamper to chips/components equipped on the circuit board. The proposed approach is to utilize the I/O physical timing characters to obtain a specified fingerprint for each specified chip on the board, and to check the validity of the chip by matching its fingerprint for later usage. To obtain the required fingerprint, an inner sampling logic is set after the I/O pins to get the timing characters reflected on the lines connected between the master chip and the slave chip to be verified. From the sampling result, the physical character associated with the slave chip is extracted and compared with the valid one. Because tampers will influence the physical character to distort the fingerprint, it has the abilities to detect tamper behaviors like chip replacement and faked signal injection. A logic analyzer and 8051-MCU based evaluation system is constructed. The test result shows that it can effectively identify the valid chip from the faked ones. Hence, the proposed approach can be deployed into the circuit board to protect the chips equipped on the board against hardware attacks.

Hash tree is a secure way to authenticate stored data. However, it is difficult to maintain a consistent state between the authentication result and data, which is necessary for permanent data storage of disk. Incremental node updating is proposed to solve such problem, it synchronizes data modification and authentication result with low cost. The reason is that the path from leaf node to root node of the tree can be very short, and each step on the path can be finished quickly as no sibling nodes are required. Thus, it greatly reduce additional disk I/O for authentication synchronization. Together with a low cost logging mechanism implemented by NVRAM, system can make fast recovery to still keep the required consistency after any failures. Related approach is elaborated, as well as testing results. Theoretical analysis and experimental simulations show that it is a practical and available way for mass data storage authentication.

To protect hard disk data confidentiality and integrity, AEIVV associates one unique IV with each disk sector; then, it applies authenticated encryption of AES-CCM to the protected sector and constructs hash tree upon IV storage. Through assuring IV to be trusted or un-tampered, data can be protected firmly. To make it an available way for disk protection, various optimizing measures are applied to quicken the running speed. With the emphasis of reducing extra latencies caused by protection, IV/MAC storage is allocated using interlaced layout to decrease seek time of disk I/O, IV checking penalty is reduced by buffering the frequently used hash tree nodes and IV/MAC values. Related approaches are elaborated, as well as experimental results. It shows that AEIVV is a practical and available way to build secure disk.

Hash tree based disk storage integrity protection suffers from performance penalty and possible losing of consistency. FI-Tree deploys a fixed-structure tree and applies incremental-hash to tree node updating to solve the difficulties of performance and consistency. The biggest advantage of FI-Tree comes from that: to allow tree nodes to be cached to optimize performance, it can maintain consistency between the tree and the protected data with low cost at the same time. Basing on FI-Tree, TNSD constructs an instance of secure disk. TNSD associates one nonce with each data block to be protected, and applies FI-Tree to ensure the nonce to be un-tampered. In such way, data protection can be fulfilled with resistance against any attacks. Related approaches are elaborated, as well as testing results. Theoretical analysis and experimental simulation show that it is a practical and available way to build secure disk.