For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the modified shortest and longest path method. The computational complexity of our algorithm is generally better than that of known algorithms in the literature. The implementation (CYCLOPSS) has been applied to an industrial chip to verify the clock schedules.

Abstract- In recent years, many new algorithms have been proposed for performing a complete timing analysis of sequential logic circuits. In this paper, we present an incremental timing analysis algorithm. When an incremental design change is made on the logic network, this algorithm will identify the portion of de-sign for which the timing is affected, and quickly derive the new arrival times and slacks. A fast incremental timing analysis is de-sirable for users doing interactive logic design. It is particularly important for a logic synthesis program, which needs to evaluate the circuit delays under many logic modifications. 1.

A hierarchical compactor, HIMALAYAS (HIerarchical MAcro LAYout ASsembler), developed for constructing big macro layouts, is discussed. The hierarchical compaction problem is formulated as an integer linear programming (ILP) problem. Two algorithms are presented to reduce the problem size, in order to make the ILP approach practical. The first algorithm reduces the number of variables to a small set of pitch variables, while the second algorithm reduces the number of equations by restricting the constraint generation within a small set of regions, called the minimum cover. These reductions bring in considerable saving in computation time for layouts with cell repetitions or cell alignments. As a result, the ILP method can be used to solve the compaction problem for very big macros. Experimental results for MCNC benchmark examples are also given.>

We investigate the modeling and solution techniques of VLSI layout compaction using the constraint graph approach under various practical design considerations. In particular, we extend the graph method to the compaction of VLSI layout with mixed grid constraints in addition to the usual minimum- and maximum-type constraints. This is a mixed integer problem. We show that it can be solved by the search of effectively longest paths, and a fast algorithm is presented

We present a global wiring algorithm used in a top-down physical design environment, i.e., macros are laid out after global wiring is done, and wires are allowed to pass through macros (the wiring-through model). The floorplan of the chip is in the form of a slicing structure. The algorithm is based on a hierarchical scheme. The final result is obtained through a series of refinement as the problem is recursively decomposed into a set of small-sized problems and then solved efficiently. The worst-case run-time for an arbitrary slicing tree (totally skewed) is O(M /sup 2/ N). When the floorplan is represented by a balanced slicing tree, the run-time of the overall algorithm is O(MN), where M is the number of macros and N the number of nets. The algorithm has been implemented in the C language and is used for chip designs. Experiments on both real and randomly generated designs show that the hierarchical router performs equally well as a flat global router in terms of wire length and wireability handling, but much faster in run-time (at least 10 times for an example with 100 macros and 1000 nets, and the gap being even larger for bigger-size problems).

We present a global wiring algorithm used in a top-down physical design environment, i.e. macros are laid out only after global wiring is done, and wires are allowed to pass through macros (wiring-through model). The floorplan of the chip is in the form of a slicing structure. The algorithm is based on a hierarchical scheme. The final result is obtained through a series of refinement as the problem is recursively decomposed into a set of small-sized problems and then solved efficiently. Given a balanced slicing tree representation of the floorplan, the worst-case running time of the overall algorithm is O(MN), where M is the number of macros and N the number of nets. The algorithm has been implemented in the C language and has been used for actual chip design. Experiments showed that the hierarchical router performs better than a flat maze type router in wireability handling, equally well in wire length, and much faster in run-time (at least 10 times for an example with 100 macros and 1000 nets, and the gap being even larger for bigger sized problems).

Logic testing of today's integrated circuits is a task of increasing difficulty as the number of circuits or transistors packed onto a single chip grows higher and higher. Exhaustive pattern testing, with adequate partitioning of logic, has been explored regarding its potential in solving the problems in test pattern generation and fault coverage. In this paper, we propose a new method of simultaneously generating exhaustive test patterns for all possible input subsets (each corresponding to an output) up tq a specified size. The method is based on the structure of linear polynomial codes and can be easily implemented by modifying existing shift-registers in an LSSD or scan path design to embody additional feedback connections. This is particularly attractive since the implementation is compatible with the approach of self-testing using pseudorandom patterns. Thus, a very reasonable strategy is to combine limited exhaustive pattern testing with pseudorandom pattern testing ini cases where complete exhaustive testing is not practical.

We develop in this paper a simple way of generating a test set which simultaneously provides exhaustive pattern testing with respect to all input subsets of a logic circuit up to a certain size. It is shown that such a test set may be formed with vectors of a particular set of weights. Main theorems and examples are established and illustrated in the binary case (for 2-value logic circuits) and then generalized to nonbinary cases (for multivalue logic circuits). Such test sets are simple in structure and become optimal in size in certain cases. It is also shown that such a test set can be effectively implemented via a scan path type shifter.

In this paper we consider an SS/TDMA system withMuplink beams andNdownlink beams, where uplink beamihas bandwidth βiand downlink beamjhas bandwidth αj. The maximum traffic which can be handled by the satellite (in any given time slot) is assumed to beK. Multiplexing and demuitiplexing are also assumed. An optimal time slot assignment algorithm to minimize the total transmission time for any given traffic demand matrix is proposed and analyzed. Other system configurations of interest are also discussed.

Encryption is used in a communication system to safeguard information in the transmitted messages from anyone other than the intended receiver(s). To perform the encryption and decryption the transmitter and receiver(s) ought to have matching encryption and decryption keys. A clever way to generate these keys is to use the public key distribution system invented by Diffie and Hellman. That system, however, admits only one pair of communication stations to share a particular pair of encryption and decryption keys, The public key distribution system is generalized to a conference key distribution system (CKDS) which admits any group of stations to share the same encryption and decryption keys. The analysis reveals two important aspects of any conference key distribution system. One is the multitap resistance, which is a measure of the information security in the communication system. The other is the separation of the problem into two parts: the choice of a suitable symmetric function of the private keys and the choice of a suitable one-way mapping thereof. We have also shown how to use CKDS in connection with public key ciphers and an authorization scheme.

In this paper we consider an SS/TDMA system withMuplink beams,Ndownlink beams, andKconnection points. We first assume that the downlink is α times faster than the uplink, and a simple time multiplexing scheme is employed. An optimal time slot assignment algorithm for anyM, N,\alpha, andK,1 \leq K \leq \min (M, \alphaN), and for any traffic matrix is presented, where optimality means achieving the minimal possible total transmission time for the given traffic matrix. The number of switching matrices generated by the algorithm never exceedsMN + K\alpha + 1. Extensive simulation results on randomly generated matrices are carried out, showing that the average number of switching matrices generated is substantially lower than the upper bound. The case when the uplink is faster than the downlink is also considered.

In this paper we consider the optimization of teleprocessing (TP) networks with concentrators. Each terminal may in general have multiple connections to several concentrators. The first part of the paper is concerned with the optimal assignment of terminals to a given set of concentrators. A sequential assignment algorithm is presented with its efficiency and optimality established. The second part of the paper is concerned with the optimal number and location of the concentrators to be installed. A generalized "ADD" algorithm is suggested. It is shown that the total cost function is convex with respect to the nwnber of concentrators installed in such an algorithm.

The cyclic distance-2 chaining of constant-weight codes has applications in A/ D conversions as well as in combinatorial problems involving the exhaustion of m-out-of-n combinations. It is shown in this paper that such a chaining can be obtained from the Gray code circuit and its transformations. Algorithms based on several theorems derived have been developed and programmed in APL.