Today, having a fast hardware platform for SoC software development prior to silicon is an important challenge to gain the time-to-market. The FPGAs offer an excellent prototyping basis for building hardware platforms since more than ten years. However, as the circuit complexity increases and project timeframes shrink, building a multi-FPGA prototype represents a real challenge from the complexity viewpoint. The paper describes the state-of-the-art mapping methodology, prototyping tools and flows, shows the most difficult mapping problems and the ways to overcome them. The paper is issued from the experience of mapping on FPGA platform of four latest highly complex ST Microelectronics SoCs ranging from 1.5 to 4 million real ASIC gates mapped to up to 9 highest capacity FPGAs.

This paper presents a multi-way FPGA partitioning method. The basic idea is similar to one proposed by Kuznar et al. (1995), but instead of using the replication and re-optimization, it takes force of the classical iterative improvement partitioning techniques. The basic effort consists in guiding the classical algorithms in their solution space exploration. This was done by introducing the cost function based on the infeasibility distance of the partitioning solution and carefully tuning the basic parameters of the classical algorithms such as definition of size constraints for feasible moves, handling solutions stack, selecting best cluster to move, etc. The proposed method obtains results comparable to the best published results, and even outperforms them for the largest benchmarks.

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The goal of this paper is to perform a timing optimization of a circuit described b y a network of cells on a target structure whose connection delays ha v ediscrete values follo wing its hierarch y. The circuits is modelled by a set of timed cones whose delay histograms allow their classification into critical, potential critical and neutral cones according to predicted delays. The floorplanning is then guided b y this cone structuring and has two innov ativ e features:first, it is shown that the placement of the elements of the neutral cones has no impact on timing results, th us a significant reduction is obtained; second, despite a greedy approach, a near optimal floorplan is achieved in a large number of examples.

This paper addresses an automatic partitioning method of adesign into several FPGAs. Although the circuit partitioningmethods have recently been significantly advanced, partitioningis commonly performed at the gate netlist level. To cope withlarge designs and explore the solution space efficiently,clustering of the logic is mandatory. In this paper, the hierarchyof the design, naturally introduced by the designer, guides thepartitioning. The basic concepts are introduced in terms of"envelope" delimiting hierarchy blocks. These concepts lead toan "envelope"-based clustering and to the proposed finalhierarchy-driven partitioning. Results are given on industrialexamples on XILINX 4000 technology.

Because the VLSI circuits complexity growth, the trend in design is towards divide-and-conquer schemes, in which circuits are composed of blocks, standard macros or custom macros. From the other side, to allow an implementation of large digital circuits, increased capacity target FPGAs are organized hierarchically. In this paper, we present a hierarchical FPGA floorplanning method which takes into account both the hierarchy of the design and the hierarchy of the target. The method aims at minimization the timing and balancing cost of the floorplan and is based on automatic detection of macro blocks and assigning them to the target FPGA hierarchical zones.