In current cryogenic temperature sensor (cryo-TS) systems, the sensing front-end and readout circuits typically operate in cryogenic and room-temperature environments, respectively. This paper proposes a scheme to integrate both the front-end devices and readout circuits of cryo-TS within the cryogenic environment to achieve lower noise, digital fan-out of temperature information, and cost reduction. We employed the silicon-germanium (SiGe) heterojunction bipolar transistors (HBT), which demonstrated excellent linearity and current gain even at cryogenic temperatures, as the sensing front end of the cryo-TS and a Zoom-ADC as its readout circuits. A redundancy bit is introduced in the cryogenic readout ADC to avoid temperature misjudgment. The design methodology and key considerations for implementing cryogenic readout analog circuits are presented. Implemented in a 65 nm CMOS process, the cryo-TS achieved a 1-point-trimmed (at 40 K) inaccuracy of ±0.54 K ($\boldsymbol {3\sigma }$) from 4 K to 70 K under a supply current of 22.13$\mu A$.

Layout design of analog integrated circuits is a time-consuming manual process with limited automation methods. Recently, advances in machine learning have opened up possibilities for automated design, making it a viable option to improve efficiency. In this paper, we present an innovative and highly effective approach to achieve automated analog circuit placement. We transform the analog placement constraints into multiple task objectives, and apply multi-task neural network learning to perform accurate placement solutions efficiently. Besides, the global position information is utilized to achieve more orderly placement. Due to the computational properties of the network, the method exhibits versatility in accommodating diverse scales of circuit netlists. Moreover, the model is trained through unsupervised learning. Compared to the supervised counterpart using many generated synthetic layout datasets, the proposed approach dramatically reduces the cost of placement data. Experimental results demonstrate that compared to SOTA works, the proposed placement learning method can achieve significant performance gains.

In recent years, analog circuits have received extensive attention and are widely used in many emerging applications. The high demand for analog circuits necessitates shorter circuit design cycles. To achieve the desired performance and specifications, various geometrical symmetry constraints must be carefully considered during the analog layout process. However, the manual labeling of these constraints by experienced analog engineers is a laborious and time-consuming process. To handle the costly runtime issue, we propose a graph-based learning framework to automatically extract symmetric constraints in analog circuit layout. The proposed framework leverages the connection characteristics of circuits and the devices’ information to learn the general rules of symmetric constraints, which effectively facilitates the extraction of device-level constraints on circuit netlists. The experimental results demonstrate that compared to state-of-the-art symmetric constraint detection approaches, our framework achieves higher accuracy and F$_1$-score.