Demo Data from EDBT 2026 / reviewers in the wild / expert
Ehsan Mohandesi
dblp:02/7644
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2016
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 1Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Interconnection networks and networks-on-chip · 44% Energy-efficient computing · 44% Processor architecture and microarchitecture · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Energy-efficient computing › voltage scaling
voltage islands |
0.2 | 1 | 2016 | Wireless NoC for VFI-Enabled Multicore Chip Design: Performance Evaluation and Design Trade-Offs · IEEE Trans. Computers 2016 |
Interconnection networks and networks-on-chip › network-on-chip design
wireless network-on-chip |
0.2 | 1 | 2016 | Wireless NoC for VFI-Enabled Multicore Chip Design: Performance Evaluation and Design Trade-Offs · IEEE Trans. Computers 2016 |
Processor architecture and microarchitecture
multicore design |
0.1 | 1 | 2016 | Wireless NoC for VFI-Enabled Multicore Chip Design: Performance Evaluation and Design Trade-Offs · IEEE Trans. Computers 2016 |
Methods — techniques the papers use, named apart from their topics
performance evaluation · 0.2design tradeoff analysis · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2016 | Wireless NoC for VFI-Enabled Multicore Chip Design: Performance Evaluation and Design Trade-OffsabstractMultiple Voltage Frequency Island (VFI)-based designs can reduce the energy dissipation in multicore chips. Indeed, by tailoring the voltages and frequencies of each VFI domain, we can achieve significant energy savings subject to specific performance constraints. The achievable performance of VFI-based multicore platforms depends on the overall communication backbone, which relies predominantly on Networks-on-Chip (NoCs). Traditionally mesh-based NoCs have been used in VFI-based systems. However, the mesh-based NoCs have large latency and energy overheads due to their inherently long multihop paths. Emerging paradigms such as the millimeter (mm)-wave small-world wireless Networks-on-Chip (mSWNoCs) have lately been observed to help reduce the impact of the communication backbone on the performance of the multicore chips. In this work, we demonstrate that not only do mSWNoC-enabled VFI designs mitigate some of the full-system performance degradation inherent in VFI-partitioned multicore designs, but they also help in eliminating it entirely for certain applications. We also demonstrate that the VFI-partitioned designs used in conjunction with a novel NoC architecture like mSWNoC can achieve significant energy savings while minimizing the impact on the performance for each application under consideration. Ryan Gary Kim, Wonje Choi 0001, Guangshuo Liu, Ehsan Mohandesi, Partha Pratim Pande, Diana Marculescu, Radu Marculescu |
IEEE Trans. Computers | 4 |
| 2009 | Protein Fold Prediction Problem Using Ensemble of Classifiers
Abdollah Dehzangi, Somnuk Phon-Amnuaisuk, Keng Hoong Ng, Ehsan Mohandesi |
ICONIP (2) | 4 |