Conventional, pre-RTL SoC architectural design space exploration does not account for the chip's floorplan. However, the power and performance of integrated CPU-GPUs are highly dependent not only on architectural specifications and workload characteristics but also on the underlying floorplan. We develop a floorplanaware system-level analysis framework for integrated CPU-GPUs and demonstrate that the overall energy efficiency can be over/under estimated by up to 25% when floorplan is not accounted for. The floorplan-aware system-level exploration tool allows us to observe interesting dependencies between architectural choices and physical design. These observations guide the framework in determining energy efficient floorplans for wide-range of workloads.

Fine grain 3D integration of commonly used components appears to be an attractive architectural solution. But finely partitioned, highly regular blocks face unique layout level challenges due to uneven scaling of Through Silicon Vias (TSVs) and circuit elements. We show that for high yielding TSVs and decreasing transistor sizes, the mismatch between the TSV dimension and the feature size affects the outcome of 3D design space exploration, especially for fine grain partitioned, highly regular microprocessor blocks such as SRAM registers and caches. For a 4-layer implementation of an SRAM register in 45nm technology, we show that improving the TSV yield from 20% to 90% requires layout modifications that worsen register's performance up to four times. Moreover, the same 4-layer register that performs three times as fast as its single layer equivalent at 20% yield becomes twice slower at 70% yield when layout effects are considered. We also explore some non-conventional physical design schemes for 3D architectural blocks in which performance deterioration is much slower even for very high TSV yields.

Long wires degrade significantly the performance of network-on-chip (NoC) communication fabric in large multicore processors. 3D network-on-chip architecture alleviates the problem of long wires, but practical limitations of CMOS technology restrict such structures to two active layers only. In this work, we study a heterogeneous 3D chip with processor cores and cache blocks implemented in CMOS and NoC fabric in VeSFET technology. Such a 3D architecture shows significant improvements in all network parameters including latency, power and energy consumption compared to existing 3D NoCs.