This paper presents a stage-level clock-gating scheme for clock power improvement. The proposed technique efficiently implements the concept of transparent pipeline which improves clocking power by dynamically making pipeline registers transparent. We developed new control scheme for transparent pipeline which can be applied to any number of pipeline stages. A low-overhead flip-flop with transparent mode is also proposed to reduce implementation overhead. The proposed clock-gating control logic is extended to pipeline collapsing which allows energy/performance trade-off through dynamic frequency scaling. Simulation results on IBM 90 nm technology show that the proposed approach has less overhead (~25%) than the previous transparent pipeline scheme and improves up to 40% of clocking power in 64-bit 7-stage pipeline over traditional stage-level clock-gating technique.

We present a fast, segment-based approach to estimate the functional coupled-noise value at the receiver pins of a net with minimal loss of accuracy. The net is suitably modeled into segments consisting of two-pi, three-pi or four-pi models. The noise contribution due to each segment on a receiver pin is then calculated. The average error of our model was less than 8% when compared with a spice-like simulator while requiring an order of magnitude less run time. This is the first work in our knowledge to use a segment-based approach for fast noise estimation that is reasonably accurate while taking into account the noise contribution at a sink pin due to coupling noise at the branches. We show that the noise on a receiver pin due to coupling nets coupled to the branches can be of the same magnitude as the noise contribution of coupling nets not coupled to the branches, and therefore cannot be ignored.

With the increase in current densities, electromigration has become a critical concern in high-performance designs. Typically, electromigration has involved the process of time-domain simulation of drivers and interconnect to obtain average, root mean square (r.m.s.), and peak current values for each wire segment. However, this approach cannot be applied to large problem sizes where hundreds of thousands of nets must be analyzed, each consisting of many thousands of RC elements. The authors propose a static electromigration analysis approach. They show that the charge transfer through wire segments of a net can be calculated directly by solving a system of linear equations, derived from the nodal formulation of the circuit, thereby eliminating the need for time domain simulation. The authors account for the different possible switching scenarios that give rise to unidirectional or bidirectional current by separating the charge transfer from the rising and falling transitions and also propose approaches for modeling multiple simultaneous switching drivers. They implemented the proposed static analysis approach in an industrial electromigration analysis tool that was used on a number of industrial circuits, including a large microprocessor.

Coupled noise analysis has become a critical issue for deep-submicron, high performance design. In this paper, we present, ClariNet, an industrial noise analysis tool, which was developed to efficiently analyze large, high performance processor designs. We present the overall approach and tool flow of ClariNet and discuss three critical large-processor design issues which have received limited discussion in the past. First, we present how the driver gates of a coupled interconnect network are represented with accurate linear models. Second, we show how to speed the analysis of large designs by using noise filters based on reduced interconnect representations and then pruning the nets coupled to a signal net. Third, we show how to incorporate logic and timing correlations into noise analysis to reduce its pessimism. We present the results from several industrial circuits, including a large high performance microprocessor design and a DSP design.

Continuous scaling of device dimensions has accelerated the power dissipation and electromigration-induced reliability degradation in integrated circuits. Submicrometer scaling increases the fraction of on-chip energy dissipated on long interconnects and buses. In addition, submicrometer-level scaling increases current density in long interconnects and buses, causing structural damage in metal lines due to electromigration (a major failure phenomenon in integrated circuits). We present algorithms for synthesizing high-reliability, low-energy microarchitectures. This can be realized by judiciously binding and scheduling the data transfers of a control-data-flow graph representation of an application onto the buses in the microarchitecture. The algorithm considers (i) correlations between data transfers, (ii) constraints on the number of buses, and (iii) area and delay.

The authors propose a method to synthesize finite state machines (FSMs) for low power. The method consists of two stages-disjunctive partitioning and selective operation. In disjunctive partitioning, the state transitions of an FSM are judiciously partitioned such that all state transitions originating from a state are assigned to one partition. This partitioning can be directed by objectives such as uniform heat distribution and hot-carrier and electromigration reliability. In the second stage, selective operation, the partitioned states are encoded such that for a given encoding for the states, only one partition is required to compute the next state encoding. This is then used to cut back on unnecessary switching, by selectively turning off all partitions except the necessary one, consequently saving on power. Of added significance, is that multiple objectives can be simultaneously tackled in the proposed approach. Since partitioning minimizes the delay (the delay is equal to the maximum delay among the partitions), the proposed method stands apart from most power minimization techniques by simultaneously minimizing both power and delay. Furthermore, objectives such as heat distribution can be used to drive the disjunctive partitioning stage. Power reductions of 50% are achievable using the proposed approach.

Abstract � Electromigration induced degradation in integrated circuits has been accelerated bycontinuous scaling of device dimensions. We present a method� ology for synthesizing high�reliability and low�energy microarchitectures at the RT level by judiciously bind� ing and scheduling the data transfers of a control data �ow graph�CDFG � representation of the application onto the buses in the microarchitecture. The proposed method accounts for correlations between data trans� fers and the constraints on the number of buses � area and delay. 1Introduction With VLSI fabrication technology reaching sub�micron device dimensions � the role of the interconnect has be� come dominant in determining the reliability of inte� grated circuits �1�. As a result of sub�micron scal� ing � current densities of 10 6 A�cm 2 or more exist in metal interconnects �3�. These current densities far exceed the threshold current densities for electromi� gration � � 500000 A�cm 2 �. Research on the DEC ALPHA CPU has shown that the electromigration median�time�to�failure MTF �de�ned as the time for 50 � of the metal lines to fail � is of the order of 10 4 �10 5 hours �1�10 years � �1 � 4�. Electromigration is predom� inantly due to the transport of conductor metal atoms caused by the momentum transferred by the electron current. If the electron current density is su�ciently high then the metal atoms get depleted from one region on the conductor and pile up at other regions. This accumulation and depletion process continues until it becomes severe enough for circuit failure. Equation 1� relates the electromigration MTF of a conductor to the current density � J � and temperature � T �9 � 10�. MTF � A J n �exp Ea�kT �1� In equation 1 � Ea is the activation energy � k is the Boltzmann�s constant and the constant A depends on the physical dimensions of the metal conductor. Ex� periments reveal that the empirical parameter n is ap� proximately 2. The current density J on a line i depends on the proba� bility pi � that the line toggles in a clock cycle as shown in equation 2.

Hot-carrier eects and electromigration are the two important failure m e chanisms that signi cantly impact the long-term reliability of high-density VLSI ICs.In this paper, we present a probabilistic switchlevel method for identifying the most susceptible hotcarrier MOSFETs and improving their hot-carrier reliability using two techniques { (i) reordering of inputs to logic gates and (ii) selective MOSFET sizing.We also show that for a given circuit, the best design in terms of hot-carrier reliability does not necessarily coincide with the best design in terms of power consumption.

We present a deterministic and provably optimal algorithm to synthesize real time, reliable multiprocessors using a heterogeneous library of N processors and L link types. For a series-parallel task graph consisting of M sub tasks and with a nested depth d, the worst-case complexity of the proposed algorithm is O(M(L+N)N/sup d/). For tree-structured task graphs, on the other hand, the algorithm runs in O(M(L+N)) time, and is also asymptotically optimum.