Pre-silicon modeling tools for characterizing power, area, and timing (PAT) have enabled numerous architectural studies, but traditional analytical and table-based models begin to exhibit limitations in their applicability as architectural design complexity increases and process technology scales below 5 nm with the emergence of advanced transistors. Previous modeling techniques typically assume static scaling factors across different designs and technology nodes, derived from small circuit design benchmarks using old processes. Consequently, they do not reflect complex design variability and nonlinear projection to advanced technology nodes. Moreover, reference logic and SRAM implementations serving as the baseline for design and technology scaling are often created using different technologies and design rules, leading to significant estimation inaccuracies that distort the relative contributions of individual components. To address these challenges, this paper introduces NPUWattch, a machine learning-based PAT modeling framework for neural accelerators. It leverages neural network regression models to learn complex nonlinear relationships in technology and design scaling based on diverse post-layout logic and SRAM design datasets formulated using unified technology libraries. To this end, we developed technology libraries from 65 nm to 2 nm, constructed and validated diverse logic and SRAM datasets, and trained neural network models using an adaptive loss function to reinforce underrepresented regions of the design space. NPUWattch is validated against the post-layout results of numerous open-source neural accelerators, and evaluation results demonstrate that NPUWattch outperforms existing tools with an average estimation error of 2.7%, offering reliable and accurate PAT estimation.

On-chip power planning is a crucial step in chip design. As process nodes advance and the need to supply lower operating voltages without loss becomes vital, the optimal design of the Power Delivery Network (PDN) has become pivotal in VLSI to mitigate IR-drop effectively. To address IR-drop issues in the latest nodes, a back-side power delivery network (BSPDN) has been proposed as an alternative to the conventional front-side PDN. However, BSPDN encounters design issues related to the pitch and resistance of through-silicon vias (TSV s). In addition, BSPDN faces optimization challenges due to the trade-off between rail and grid IR-drop, particularly in the effectiveness of uniform grid design patterns. In this study, we introduce a design framework that utilizes reinforcement learning to identify optimized grid width patterns for individual VLSI designs on the silicon back-side, aiming to reduce IR-drop. We have applied our design approach to various benchmarks and validated its improvement. Our results demonstrate a significant improvement in total IR-drop, with a maximum improvement of up to −19.0% in static analysis and up to −18.8% in dynamic analysis, compared to the conventional uniform BSPDN.

The semiconductor foundries are now mass-producing 3nm transistors. In this trend, many studies on 2nm node report the potential of future transistors such as forksheet FET (FSFET) from the device perspective. However, only a few studies report the impact of advanced transistors at the full-chip level. Thus, this study focuses on enlightening the potential of FSFET at the full-chip level in the 2nm process compared to the 3nm node currently in mass production. To do this, we present FS2K, the first public 2nm technology library in FSFET, which provides the following results: 1) The simple scaling with no variation in devices or interconnect achieves only about 10% power reduction and area reduction in 2nm processes for FSFET and Nanoshet FET (NSFET). 2) An optimal performance improvement in a 2nm node requires FSFET to be designed in a 4T standard cell that is 1-track reduced from 3nm. Our 2nm 4T-FSFET design achieves -29.5% area reduction and -31.9% power reduction compared to the existing 3nm process. Thus, we emphasize the importance of optimization not only in the device but also in the cell layout for future processes.

This article explores the threat posed by Hardware Trojans (HTs), malicious circuits clandestinely embedded in hardware akin to software backdoors. Activation by attackers renders these Trojans capable of inducing malfunctions or leaking confidential information by manipulating the hardware’s normal operation. Despite robust software security, detecting and ensuring normal hardware operation becomes challenging in the presence of malicious circuits. This issue is particularly acute in weapon systems, where HTs can present a significant threat, potentially leading to immediate disablement in adversary countries. Given the severe risks associated with HTs, detection becomes imperative. The study focuses on demonstrating the efficacy of deep learning-based HT detection by comparing and analyzing methods using deep learning with existing approaches. This article proposes utilizing the deep support vector data description (Deep SVDD) model for HT detection. The proposed method outperforms existing methods when detecting untrained HTs. It achieves 92.87% of accuracy on average, which is higher than that of an existing method, 50.00%. This finding contributes valuable insights to the field of hardware security and lays the foundation for practical applications of Deep SVDD in real-world scenarios.

The imminent rise in data consumption and the physical constraints of current advanced CMOS scaling hasten the end of the projection to the binary system. For a breakthrough of these issues, the ternary system, known for its superior efficiency in expressing numbers (closest to$\mathrm {e}\approx ~2.7183$) has garnered considerable attention. Among the ternary studies reported, the anti-ambipolar transistor (AAT) is acquiring attention thanks to its unique negative differential resistance (NDR) and anti-ambipolar characteristics (AAC). Moreover, easy-to-fabricate inkjet-printing based AAT was introduced. Therefore, in this paper, we propose a practical design methodology (‘$\mathbf {T^{3}L:} $The Tri-transistor Ternary Logic’) and a set of novel ternary logic based on inkjet-printed AATs and CMOSs. In detail, 1) We propose balanced ternary full adders (BTFA) and prove that inkjet-printed AATs and CMOSs are highly capable of implementing any kind of ternary logic. 2) We propose two design methodologies for ternary logic design: NDR-based Design Method I and AAC-based Design Method II. 3) We present optimization methodology for inkjet-printed ternary circuit stability and provide circuitry to secure sufficient noise margin. We provide a highly-compact BTFA design that requires only 64 transistors and an ultra-low-power BTFA design that reduces power by 84.7% to 98.8% compared to the previous designs.

The predicted end of scaling and the exponential increase of user data in the era of the connected world are asking whether the current binary systems in CMOS can successfully provide solutions to the expected challenges. Regarding these challenges, ternary systems are showing a high potential to provide solutions to these known issues. In detail, the tunnelling-based MOSFET (T-CMOS) is reported as promising compared to any other ternary devices studied. However, despite the potential, studies lack how a complete system can be designed in actual T-CMOS-based circuitry. Therefore, in this paper, we provide a holistic study of how T-CMOS-based circuits can be designed. In detail, 1) we provide a pathway to designing a balanced ternary full adder and provide the fundamental of how combinational ternary logic can be designed in T-CMOS. 2) We present various sequential ternary logic based on T-CMOS. 3) We present various circuit techniques that could enhance the performance of combinational and sequential ternary logic. Based on our study, we provide the first balanced ternary adder that the transistor count is only 42 and enhance the operating frequency of the T-CMOS-based ternary system by$5.6\times $to$58.5\times $.

Nanosheet FETs (NSFETs) are attracting attention as promising devices that can replace FinFETs beyond the 5-nm node. Despite the importance of the devices, few studies analyze the impact of NSFETs at the block-level. In this article, we introduce NS3K, the first 3-nm NSFET standard cell library, and examine the results on a block-level scale. In addition to the overall process of designing a full library, we extended the scope of the buried power rail (BPR) to better layout designs. We showed that BPR, originally proposed to overcome power delivery problems, is also an effective solution for standard cell hegith reductions. Using BPR, we highlight that 4-track height standard cell designs have a negligible impact on power delivery and signal routing. Overall chip results show that the 3-nm NSFET outperforms the 5-nm FinFET by −27.4% in power, −25.8% in total wirelength, −8.5% in the number of cells, −47.6% in area, and 34.7% performance, respectively, owing to better device performance and interconnect scaling. However, careful device/layout designs and new interconnect structures must be applied to continue the scaling trend and maximize the advantages of 3-nm technology.

Complementary field-effect transistor (CFET) is a future transistor type with a high potential to be used beyond 3-nm technology nodes. Despite its high future value, studies related to CFETs mostly focused on the device aspects. In other words, the path of CFET full-chip IC design is not fully demystified, knowing that various design factors/steps (such as schematic, layout, parasitics, design flow) must be considered on top of device traits for full-chip level IC. Therefore, this study focuses on enlightening the remaining factors/steps for full-chip IC design. In detail, we notify the importance of parasitics from various aspects of CFET design and provide optimization solutions. Compared to nanosheet FET (NSFET) on the full-chip scale, CFET shows a reduction of the area by −48.2%, power by −29.4%, total wirelength by −32.5%, and the number of cells by −18.1%.

Nanosheet FETs (NSFETs) are expected to be the post-FinFET device in the technology nodes of 5 nm and beyond. However, despite the high potential of NSFETs, few studies report the impact of NSFETs in the digital VLSI’s perspective. In this paper, we present a study of NSFETs for the optimal standard cell (SDC) library design and pin accessibility-aware layout for less routing congestion and low power consumption. For this objective, we present five novel methodologies to tackle the pin accessibility issues that rise in SDC designs in extremely-low routing resource environments (4 tracks) and emphasize the importance of local trench contact (LTC) in it. Using our methodology, we improve design metrics such as power consumption, total area, and wirelength by -11.0%, -13.2%, and 16.0%, respectively. By our study, we expect the routing congestion issues that additionally occur in advanced technology nodes to be handled and better full-chip designs to be done in 3 nm and beyond.

In recent decades, the performance of binary computers has escalated through transistor scaling. However, due to the impotent forecasts of transistor scaling, ternary systems are regaining attention. Among many ternary device candidates, a passive device called memristor that is based on resistance switching is considered a good candidate when integrated with MOSFETs. Therefore, in this paper, we design various terna-ry logic based on memristors and MOSFETs from primitive logic to sequential logic and perform a thorough diagnosis for circuit design. We highlight design issues that should be resolved (e.g., signal distortion and high static current) and present practical solutions such as “Strength Design.” Then, we report a proper design methodology of sequential circuits considering the spike phenomena of memristor-based gates. We present 16 novel ternary logic cells and circuitry, including the design of the first balanced ternary full-adder (TFA) and memristor-based ternary pulsed-latch (MTPL). By our TFA, we emphasize that it is possible to design the most practical ternary circuits using memristors and MOSFETs. Our TFA uses 97 transistors and 87 memristors, which is the most reasonable TFA design that has the highest potential to be implemented in the near future. Besides, the proposed MTPL uses 16 transistors and 10 memristors, and it occupies only 72.7% of the silicon area, compared to the master-slave ternary flip-flop.

Nanosheet FETs (NSFETs) are expected as future devices that replace FinFETs beyond the 5nm node. Despite the importance of the devices, few studies report the impact of NSFETs in the full-chip level. Therefore, this paper presents NS3K, the first 3nm NSFET library, and presents the results in a full-chip scale. Based on our results, 3nm NSFET reduces power by -27.4%, total wirelength by -25.8%, number of cells by -8.5%, and area by -47.6% over 5nm FinFET, respectively, due to better devices and interconnect scaling. However, careful device/layout designs followed by routing-resource considering standard cells are required to maximize the advantages of 3nm technology.

Existing transistor-level monolithic 3D (T-M3D) standard cell layouts are based on the folding scheme, in which the pull-down network is simply folded and placed on top of the pull-up network. In this paper, we propose a new layout method, the stitching scheme, targeted towards improved cell performance and power integrity. We perform extensive analysis on each layout scheme and evaluate the timing/power benefits of the stitching scheme. Since the ground and power rails overlap in the T-M3D layouts with the folding scheme, we also present a design methodology for the power delivery network of folding T-M3D ICs to evaluate the impact of the T-M3D cell layout scheme on static power integrity. Compared to 2D ICs at iso-performance, stitching T-M3D ICs show a maximum of 6% power savings, 44% area savings with only 1% more static IR-drop in the 14nm technology node while folding T-M3D ICs undergo serious degradation in static power integrity, causing a reliability issue.

Low power is considered as the driving force for 3-D ICs, yet there have been few thorough design studies on how to reduce power in 3-D ICs. In this paper, we discuss computer-aided design techniques and design methodologies to reduce power consumption in 3-D IC designs using a commercial grade CPU core (OpenSPARC T2 core). To demonstrate power benefits in 3-D ICs, four design techniques are explored: 1) 3-D floorplanning; 2) metal layer usage control for intrablock-level routing; 3) dual-Vth design; and 4) functional unit block (FUB) folding. The benefits and challenges of multiple FUB folding are also discussed. Finally, the through-silicon via technology scaling impact on FUB folding and 3-D power benefit is examined. With the aforementioned methods combined, our 2-tier 3-D designs provide up to 52.3% reduced footprint, 27.9% shorter wirelength, 35.4% decreased buffer cell count, and 27.8% power reduction over the 2-D counterpart under the same performance.

Low-power is one of the key driving forces in modern very large scale integration systems. Recent studies show that 3-D integrated circuits (ICs) offer a significant power saving over 2-D ICs. However, these studies are mainly limited to two-tier (2-tier) designs. Thus, in this paper, we extend our target to three-tier (3-tier) 3-D ICs. This paper first shows that the one additional tier available in 3-tier 3-D ICs does offer more power saving compared with their 2-tier 3-D IC counterparts, but more careful floorplanning, through-silicon via management, and block folding considerations are required. Second, we find that the 3-tiers can be bonded in several different ways: 1) face-to-back only; 2) face-to-face and face-to-back combined; and 3) back-to-back and face-to-face combined. This paper shows that these choices pose additional challenges in design optimizations for more power saving. Lastly, we develop effective computer-aided-design solutions that are seamlessly integrated into commercial 2-D IC tools to handle 3-tier 3-D IC power optimization under various bonding style options. With our low-power design methods combined, our 3-tier 3-D ICs provide -14.8% more power reduction over 2-tier 3-D ICs, and -36.0% over 2-D ICs in microprocessor cores under the same performance. In full-chip microprocessors, our 3-tier 3-D ICs provide -27.2% more power reduction over 2-D ICs.

Through-silicon-via (TSV)-to-TSV coupling is a new phenomenon in 3-D ICs, and it becomes a significant source of signal integrity problems. The existing studies on its extraction and analysis, however, become inaccurate when handling more than two TSVs on full-chip scale. In this paper, we investigate the multiple TSV-to-TSV coupling issue and propose a model that can be efficiently used for full-chip extraction. Then, we perform an analysis on the impact of TSV parasitics on coupling and delay. Unlike the common belief that only the closest neighboring TSVs affect the victim, this paper shows that nonneighboring aggressors also cause nonnegligible coupling noise. Based on these observations, we propose an effective method of reducing the overall coupling level.

Face-to-face (F2F) bonded 3D ICs are promising design solutions. However, because of the short die-to-die distance, direct coupling between the metal layers of the top and bottom dies introduces severe signal integrity problems that call for accurate extraction. This study is the first to demonstrate and compare three parasitic extraction methods of F2F-bonded 3D ICs. One is traditional die-by-die extraction, which cannot handle inter-die coupling and E-field sharing. We propose another method, holistic extraction, which treats all layers from both dies simultaneously and captures all inter-die coupling at the cost of high Layout Versus Schematic (LVS) complexity. We also propose an in-context extraction method that accounts for interface layers between dies. Carefully handling double-counting and surface layers issues, in-context extraction is LVS-friendly without losing accuracy. Full-chip analyses show that both of our extraction methods are highly accurate and able to handle various metal layers in several process nodes. It also corrects timing, power, and signal integrity errors introduced by die-by-die extraction. In-context extraction with two interface layers is highly accurate and efficient with an error of 0.9% for total ground capacitance and 0.8% for total coupling capacitance.

Low-power is one of the key driving forces in modern VLSI systems. Several recent studies show that 3D ICs offer significant power savings over 2D ICs, primarily due to wirelength and buffer saving. However, these existing studies are mainly limited to 2-tier designs. In this paper, our target is extended to 3-tier 3D ICs. Our study first shows that the one additional tier available in 3-tier 3D ICs does offer more power saving compared with their 2-tier 3D IC counterparts, but more careful floorplanning, through-silicon via (TSV) management, and block folding considerations are required. Second, we find that the three tiers can be bonded in different ways: (1) face-to-back only and (2) face-to-face and face-to-back combined. Our study shows that these choices pose additional challenges in design optimizations for more power saving. Lastly, we develop effective CAD solutions that are seamlessly integrated into commercial 2D IC tools to handle 3-tier 3D IC power optimization under various bonding style options. With our low-power design methods combined, our 3-tier 3D ICs provide -14.8% more power reduction over 2-tier 3D ICs and -36.0% over 2D ICs under the same performance.

This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2$\micro\hbox{m}$-diameter, 6$\micro \hbox{m}$-height through-silicon vias (TSVs) and$3.4\nbsp\micro\hbox{m}$-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks.

Low power is widely considered as a key benefit of 3D ICs, yet there have been few thorough design studies on how to maximize power benefits in 3D ICs. In this paper, we present design methodologies to reduce power consumption in 3D ICs using a large-scale commercial-grade microprocessor (OpenSPARC T2). To further improve power benefits in 3D ICs on top of the traditional 3D floorplanning, we study the impact of block folding and bonding styles. We also develop an effective method to place face-to-face vias for our 2-tier 3D design for power optimization. With aforementioned methods combined, our 3D designs provide up to 20.3% power reduction over the 2D counterpart under the same performance.

This paper presents a silicon effect-aware multiTSV model. Through-silicon-via (TSV) depletion region, silicon substrate discharging path and electrical field distribution around TSV neighbor are modeled and studied in full-chip design. Verification with field solver and full-chip TSV-to-TSV coupling analysis in both the worst case and the average case show this model is accurate and efficient. It is found that 3-D nets receive more noise than their 2-D counterparts due to TSV-to-TSV coupling. To alleviate this coupling noise on TSV nets, two new optimization methods are investigated. One way is to utilize guard rings around the victim TSV so as to form a stronger discharging path, an alternative approach is to adopt differential signal transmission to improve noise immunity. These techniques have been implemented on 3-D IC designs with TSVs placed regularly or irregularly. Full-chip analysis results show that our approaches are effective in noise reduction with small area overhead.

TSV-to-TSV coupling is a new parasitic element in 3D ICs and can become a significant source of signal integrity problem. Existing studies on its extraction, however, becomes highly inaccurate when handling more than two TSVs on full-chip scale. In this paper we investigate the multiple TSV-to-TSV coupling issue and propose an accurate model that can be efficiently used for full-chip extraction. Unlike the common belief that only the closest neighboring TSVs affect the victim, our study shows that non-neighboring aggressors also cause non-negligible impact. Based on this observation, we propose an effective method of reducing the overall coupling level in multiple TSV cases.

In this paper, we present a multiple-TSV based TSV-to-TSV coupling model and extraction methods that consider the impact of depletion region, the silicon substrate effect, and the electrical field distribution around TSVs. Our studies show that these factors have a significant impact on the individual and full-chip scale TSV-to-TSV coupling. Our effort leads to a simplified coupling model that is accurate and efficient on timing, power, and signal integrity in full-chip scale. In order to alleviate the coupling noise in full-chip level 3DIC, we propose grounded guard rings that are more effective than grounded TSV insertion. Results show that our approach reduces coupling noise on TSV nets up to 27.3% with only 7.65% area overhead.

This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed based on the proposed coupling model. Analysis results show that TSVs cause significant coupling noise and timing problems despite that TSV count is much smaller compared with the gate count. Two approaches are proposed to alleviate TSV-to-TSV coupling, namely TSV shielding and buffer insertion. Analysis results show that both approaches are effective in reducing the TSV-caused-coupling and improving timing.