The emergence of new applications in high-performance computing is driving the need for more efficient computing machines. As supercomputer architectures become increasingly complex, the combinatorial explosion of design spaces and the time-consuming nature of design simulations lead to challenging design space exploration problems. This work introduces an automated search framework to achieve power-performance-area efficient Arm Neoverse V1 processor designs. Based on multi-objective Bayesian optimization, we propose a new exploration algorithm named SEBO by enhancing the three main stages of the optimization. Experimental results show that SEBO can not only compete with the top state-of-the-art baseline algorithms, but also outperforms them in terms of the quality and diversity of the returned Pareto-optimal designs.

NET4EXA aims to develop a next-generation high-performance interconnect for HPC and AI systems, addressing the increasing demands of large-scale infrastructures, such as those required for training Large Language Models. Building upon the proven BXI (Bull eXascale Interconnect) European technology used in TOP15 supercomputers, NET4EXA will deliver the new BXI release, BXIv3, a complete hardware and software interconnect solution, including switch and network interface components. The project will integrate a fully functional pilot system at TRL 8, ready for deployment into upcoming exascale and post-exascale systems from 2025 onward. Leveraging prior research from European initiatives like RED-SEA, the previous achievements of consortium partners and over 20 years of expertise from BULL, NET4EXA also lays the groundwork for the future generation of BXI, BXIv4, providing analysis and preliminary design. The project will use a hybrid development and co-design approach, combining commercial switch technology with custom IP and FPGA-based NICs. Performances of NET4EXA BXIv3 interconnect will be evaluated using a broad portfolio of benchmarks, scientific scalable applications, and AI workloads.

Integrated Circuits (IC) are increasingly present in our daily lives through various everyday objects. Many third-party companies are involved during their manufacturing process. It introduces many threats to the ICs' manufacturing, such as IP piracy and Hardware Trojans. Strong Logic Locking methodology is generally used to protect from IC piracy, such as counterfeiting or reverse engineering, and against Hardware Trojans insertion; however, the lack of automated tools fully integrated into a CAD flow limits the integration of countermeasures. This paper proposes mathematical models on the Strong Logic Locking method to optimize the security and an automatic security design inserted in an open CAD flow. We implemented an exact algorithm to maximize the security measure while implementing a strategy to minimize the impact of delay and area on the circuit. This algorithm is a custom branch and bound based on the mathematical model developed in this paper. In addition, we propose a strategy to limit the impact of countermeasures on the delay. Furthermore, our approach takes place inside a standard open CAD flow after logic synthesis to be as generic as possible. The experiments carried out that security can be added in a standard open CAD flow with a reasonable computation time and a limited impact on the circuit. Our security measure is more precise than the previous one, with a limited area overhead defined by a user. The increase of the critical path is less than 7% for large benches with a limit of 10% area overhead.

Finding a suitable set of controllers to which a large set of control functions with different safety levels can be assigned, while minimizing cost, is a significant task during the design of the operational control system of a critical process, such as a power plant. This task is currently performed by experts and extremely time-consuming, which explains why its automation is a real concern. This paper shows first that the above-mentioned assignment problem can be identified as a multiple-choice vector bin packing (BP) with conflicts problem, a combination of different variants of the well-known 1-D BP problem. Such a problem is known to be strongly NP-hard and exact techniques to solve it on large-sized examples are too time and/or space-consuming because of the combinatorial explosion. To solve this problem in polynomial time, this paper proposes a fast heuristic based on a first-fit decreasing approach. Two strategies to perform this heuristic and several criteria to rank the functions before assignment are defined. These strategies and criteria are then compared on the basis of numerous experiments. These experiments show that the proposed heuristic scales well and provides results that are very close to optimum; the difference in the worst case is less than 1%.

Because of the multiplication of multi-core architecture, dataflow programming languages regained interest during the last years. In the case of massively multi-core embedded system architectures, the computation of throughput is used for buffer sizing under time constraints. This paper introduces an approximate method for the throughput evaluation for cyclostatic dataflow graphs.

Cyclo-Static DataFlow Graphs (CSDFG in short) is a formalism commonly used to model parallel applications composed by actors communicating through buffers. The liveness of a CSDFG ensures that all actors can be executed infinitely often. This property is clearly fundamental for the design of embedded applications.

The design of streaming applications (e.g. multimedia or network packet processing) must consider several optimizations such as the minimization of the whole surface of the memory needed on a Chip. The problem tackled in this paper is the minimization of the whole surface of the memory needed to reach a minimum fixed throughput. The application is modelled using a Marked Timed Weighted Event Graphs (in short MTWEG), which is a subclass of Petri nets. Transitions correspond to specific treatments and places model buffers for data transfers. It is assumed that transitions are periodically fired with a fixed throughput. The problem is first mathematically modelled using an Integer Linear Program. We then study for a unique buffer the optimum throughput according to its capacity. A polynomial simple algorithm that minimizes the overall surface of memory for a fixed throughput is derived when there is no circuit in the initial MTWEG, which corresponds to a wide class of applications. We prove in this case that the capacities of every buffer may be optimized independently. For general MTWEG, the problem is NP-Hard and an original polynomial 2-approximation algorithm is presented. For practical applications, the solution computed is very close to the optimum.