Semiconductor supply chain vulnerability presents a significant obstacle to creating reliable systems. At various phases of the Integrated Circuit (IC) design life-cycle, malicious modifications, known as Hardware Trojans (HTs), can be introduced. Logic testing, a widely recognized approach for Automatic test pattern Generation (ATPG) in HT detection, encounters substantial challenges due to the vast complexity of the search space, making it impractical and leading to inadequate trigger coverage. This paper proposes a Particle Swarm Optimization (PSO) based method that leverages information on effective inputs to facilitate the detection of conditionally triggered ultra-small HTs. An evaluation of the technique on ISCAS-85 benchmarks reveals substantial improvements in trigger coverage and a notable reduction in runtime compared to state-of-the-art methods.

The global distribution of the semiconductor supply chain has heightened the risk of hardware Trojans (HTs), small malicious circuits that adversaries may embed during various stages of the system-on-chip (SoC) design process. Frequently implanted by untrusted third parties, these HTs can operate covertly and, when activated, pose a serious threat to the integrity, performance, and functionality of the system. Although there are promising test generation techniques for HT detection, they face two significant practical limitations: a lack of scalability for large designs and insufficient trigger coverage. The effective detection of HTs requires the application of appropriate test vectors. This paper introduces PATROL, a novel algorithm that combines Particle Swarm Optimization (PSO) and Genetic Algorithms (GA) within a scalable framework for the detection of HTs. This framework employs Automated Test Pattern Generation (ATPG)-based activation to achieve high trigger coverage. This approach significantly accelerates the convergence towards a solution while substantially improving the solution accuracy. Our experimental results demonstrate that our proposed method is more than 43 times faster and achieves an average increase in trigger coverage of more than 34%, significantly outperforming state-of-the-art test generation techniques for Trojan detection.

This paper presents FORTUNE, a hardware-agnostic fault tolerance technique for DNNs that leverages quantization to enhance reliability without significant performance overhead. Unlike conventional methods like Triple Modular Redundancy (TMR), which are computationally expensive, the proposed approach uses memory savings from quantization to protect the critical Most Significant Bit, improving fault tolerance in Deep Neural Networks (DNNs). Memory utilization has been reduced by 37.5% across all networks, with vulnerability in AlexNet reduced by 56% compared to the 8-bit version and 84% compared to the unprotected 3-bit version. These improvements come with only a minor increase in execution time of less than 3%. Using AlexNet as an example demonstrates how our approach effectively enhances memory utilization and resilience while causing only a minimal increase in execution time.

Multiplication is the most resource-hungry operation in the neural network’s processing elements. In this paper, we propose an architecture of a novel adaptive fault-tolerant approximate multiplier tailored for ASIC-based DNN accelerators. AdAM employs an adaptive adder relying on an unconventional use of the leading one position value of the inputs for fault detection through the optimization of unutilized adder resources. The proposed architecture uses a lightweight fault mitigation technique that sets the detected faulty bits to zero. The hardware resource utilization and the DNN accelerator’s reliability metrics are used to compare the proposed solution against the triple modular redundancy (TMR) in multiplication, unprotected exact multiplication, and unprotected approximate multiplication. It is demonstrated that the proposed architecture enables a multiplication with a reliability level close to the multipliers protected by TMR utilizing 63.54% less area and having 39.06% lower power-delay product compared to the exact multiplier.

Assertion-based verification is a promising method that uses predefined rules, known as assertions, to check the functionality of hardware designs. The manual assertion definition is time-consuming and requires expert knowledge. Automatic assertion mining is gaining acceptance as a trustworthy method for assertion definition. Some automatic assertion miners extract assertions from simulation traces of the design, but the quality of mined assertions depends on the coverage of the stimuli used to generate the traces. Existing stimuli generation methods are either random or exhaustive. A random approach can only cover some design behavior, resulting in incomplete assertions. On the other hand, an exhaustive approach can cover all the design behavior but produces lengthy simulation traces that cause a high overhead for the miner. We propose a novel approach for stimul generation based on constraint random verification. A set of user-defined metrics then examines the generated stimuli to measure how much of the design specification has been exercised by the verification environment. Our approach uses a coverage model that defines, collects, and analyzes the design’s functionalities and identifies the gaps in the verification. The assertions generated by the proposed method have been compared with a well-known assertion miner, GoldMine. The result showed that our method detects $\mathbf{2 0 . 6 3 \%}$ more faults in the design than GoldMine in a shorter time. Moreover, it produces assertions that are about $\mathbf{7 9 \%}$ more effective.

Recent advancements in machine learning achieved by Deep Neural Networks (DNNs) have been significant. While demonstrating high accuracy, DNNs are associated with a huge number of parameters and computations, which leads to high memory usage and energy consumption. As a result, deploying DNNs on devices with constrained hardware resources poses significant challenges. To overcome this, various compression techniques have been widely employed to optimize DNN accelerators. A promising approach is quantization, in which the full-precision values are stored in low bit-width precision. Quantization not only reduces memory requirements but also replaces high-cost operations with low-cost ones. DNN quantization offers flexibility and efficiency in hardware design, making it a widely adopted technique in various methods. Since quantization has been extensively utilized in previous works, there is a need for an integrated report that provides an understanding, analysis, and comparison of different quantization approaches. Consequently, we present a comprehensive survey of quantization concepts and methods, with a focus on image classification. We describe clustering-based quantization methods and explore the use of a scale factor parameter for approximating full-precision values. Moreover, we thoroughly review the training of a quantized DNN, including the use of a straight-through estimator and quantization regularization. We explain the replacement of floating-point operations with low-cost bitwise operations in a quantized DNN and the sensitivity of different layers in quantization. Furthermore, we highlight the evaluation metrics for quantization methods and important benchmarks in the image classification task. We also present the accuracy of the state-of-the-art methods on CIFAR-10 and ImageNet. This article attempts to make the readers familiar with the basic and advanced concepts of quantization, introduce important works in DNN quantization, and highlight challenges for future research in this field.

Previous efforts in gene network reconstruction have mainly focused on data-driven modeling, with little attention paid to knowledge-based approaches. Leveraging prior knowledge, however, is a promising paradigm that has been gaining momentum in network reconstruction and computational biology research communities. This paper proposes two new algorithms for reconstructing a gene network from expression profiles with and without prior knowledge in small sample and high-dimensional settings. First, using tools from the statistical estimation theory, particularly the empirical Bayesian approach, the current research estimates a covariance matrix via the shrinkage method. Second, estimated covariance matrix is employed in the penalized normal likelihood method to select the Gaussian graphical model. This formulation allows the application of prior knowledge in the covariance estimation, as well as in the Gaussian graphical model selection. Experimental results on simulated and real datasets show that, compared to state-of-the-art methods, the proposed algorithms achieve better results in terms of both PR and ROC curves. Finally, the present work applies its method on the RNA-seq data of human gastric atrophy patients, which was obtained from the EMBL-EBI database. The source codes and relevant data can be downloaded from: https://github.com/AbbaszadehO/DKGN.

In this paper, we demonstrate the feasibility of building a memristor-based approximate accelerator to be used in cooperation with general-purpose ×86 processors. First, an integrated full system simulator is developed for simultaneous simulation of any multicrossbar architecture as an accelerator for ×86 processors, which is performed by coupling a cycle accurate Marss ×86 processor simulator with the Ngspice mixed-level/mixed-signal circuit simulator. Then, a novel mixedsignal memristor-based architecture is presented for multiplying floating-point signed complex numbers. The presented multiplier is extended for accelerating convolutional neural networks and finally, it is tightly integrated with the pipeline of a generic ×86 processor. To validate the accelerator, first it is utilized for multiplying different matrices that vary in size and distribution. Then, it is used as an accelerator for accelerating the tiny-dnn, an open-source C++ implementation of deep learning neural networks. The memristor-based accelerator provides more than 100× speedup and energy saving for a 64 × 64 matrixmatrix multiplication, with an accuracy of 90%. Using the accelerated tiny-dnn for the MNIST database classification more than 10× speedup and energy saving along with 95.51% pattern recognition accuracy is achieved.

Bias Temperature Instability (BTI) and process variation introduce remarkable unpredictability to Custom Instructions (CIs) manufactured at nano-scale technology. Moreover, shrinking the feature size to nanometer levels makes soft error another critical issue of CIs. To tackle these factors, we propose a reliability-aware cross-layer CI screening method. By adding an intermediate phase between the CI generation and CI selection phases, this method enables designers to prune the outputs of the generation phase in order to guarantee that synthesized CIs meet the required reliability constraints. For this purpose, a holistic framework is developed to analyze the combined effects of the BTI and process variation as well as the soft error on the CIs by making a link between circuit-level and system-level information. Based on this information collected from different layers of abstraction, the screening method prunes those CIs which cannot meet the reliability constraints. Experiments illustrate that BTI-unaware CI selection techniques may not meet the desired lifetime because of BTI-induced delay shift of CIs. Moreover, according to the results, a remarkable percentage of CIs is vulnerable to soft error and should not be fed into CI selection phase.

This paper describes a methodology for analyzing the vulnerability of custom instructions against the electronic faults, considering different operations and the custom instruction graph topology. Our approach enables designers to optionally constrain the operand types and also the custom functional unit structure to reach an acceptable vulnerability. We have developed a framework to evaluate the desired goal. The presented framework explores the effects of different operations and their dependencies on overall vulnerability of the custom functional units. Our experiments show that, in most cases, custom functional units with similar speed-ups in performance present different vulnerability to soft errors.

Today circuits are becoming more vulnerable to electronic noises and reliable system design has emerged as a key challenge to embedded system design. Logic fault in terms of soft errors or transient faults are now a serious problem for embedded processors. Recent developments in customized embedded processors significantly focus on improving the performance and area of the processor by augmenting it with application specific custom functional units that implement custom instructions. This paper analyzes the effect of type, order, and bit-width of the operations of different custom instruction sub-graphs on the vulnerability of extensible processors. We have developed a framework for studying the effects of different operations and their dependencies on overall vulnerability of the custom functional units and our experiments show that, in most cases, similar custom functional units could have different vulnerabilities to soft errors. Our approach enables designers to optionally constrain the operand types and also the custom functional unit structure to reach an acceptable vulnerability.

Advances in silicon technology and shrinking the feature size to nanometer scale make unreliability of nano devices the most important concern of fault-tolerant designs. Soft error analysis has been greatly aided by the concept of architectural vulnerability factor (AVF) and architecturally correct execution (ACE). In this work, we exploit the techniques of AVF analysis to introduce the instruction-level vulnerability metric for software reliability analysis. The proposed metric can be used to make judgments about the reliability of different programs on different processors with regard to architectural and compiler guidelines for improving the processor reliability.