This paper presents a new performance and routability driven router for symmetrical array based field programmable gate arrays (FPGAs). The objectives of our proposed routing algorithm are two-fold: (1) improving the routability of the design (i.e., minimizing the maximum required routing channel density) and (2) improving the overall performance of the design (i.e., minimizing the overall path delay). Initially, nets are routed sequentially according to their criticalities and routabilities. The nets/paths violating the routing-resource and timing constraints are then resolved iteratively by a rip-up-and-rerouter, which is guided by a simulated evolution based optimization technique. The proposed algorithm considers the path delays and routability throughout the entire routing process. Experimental results show that our router can significantly improve routability and reduce delay over many existing routing algorithms.

Article A performance and routablity driven router for FPGAs considering path delays Share on Authors: Yuh-sheng Lee Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 30043, R.O.C. Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 30043, R.O.C.View Profile , Allen C.-H. Wu Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 30043, R.O.C. Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 30043, R.O.C.View Profile Authors Info & Claims DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation ConferenceJanuary 1995 Pages 557–561https://doi.org/10.1145/217474.217588Online:01 January 1995Publication History 30citation177DownloadsMetricsTotal Citations30Total Downloads177Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

We describe a routing method for the design of a class of RAM-based field programmable gate arrays (FPGA). We model the interconnect resources as a graph. A routing solution is represented as a set of disjoint trees, each connecting all terminals of a net, on the graph. An expansion router is used for connecting a net. Initially, nets are connected independently of one another. Conflicts among nets over the usage of interconnect resources are resolved iteratively by a rip-up and rerouter, which is guided by a simulated evolution-based optimization technique. The proposed approach has been implemented in a program called TRACER-fpga. As compared with CGE and SEGA, TRACER-fpga in general requires fewer routing tracks at the expense of longer wiring delay. It is suitable for low-speed applications such as hardware emulation.>