A VLSI architecture for performing electrocardiogram (ECG) data compression is presented. The goals of the chip are to improve both the speed and the density as compared to an off-the-shelf implementation. The complex control sections of the chip were synthesized from a functional description into standard cells, while critical-path arithmetic sections were custom designed. This mix of full custom and standard cell design allows for a trade-off between design time and area, with no penalty in speed performance. The resulting silicon chip, implemented in 1.1 mu m CMOS technology, is useful for ECG data collection, compression, and analysis.>

An efficient mapping from a tree structure into a pipelined array of 2log N states is presented for processing an N*N image. In the proposed mapping structure the identification of the information growing property inherent in feature-extraction algorithms allows bit-level concurrency to be exploited in the architectural design. Accordingly, the design of each staged pipelined processor is simplified.>

The authors present a high-performance VLSI architecture for two-dimensional (2-D) digital signal processing applications. The architecture uses a specially designed digital signal processor (DSP) as a node in a multiprocessor system for real-time or near-real-time 2-D signal processing. The DSP is custom-designed and has a throughput of two multiplications and three additions in a single cycle. It has wavefront-array-processor properties and operates asynchronously in a multiprocessor system. This architecture extends the concept of using a single processor to the use of a multiprocessor system.>

Characteristics and constraints of real-time geometric-feature extraction are discussed. Extracting geometric features from a digital image can be characterized as a computation-intensive task in the environment of a real-time automated vision system. Such tasks require algorithms with a high degree of parallelism and pipelining under the raster-scan I/O constraint. Using the divide-and-conquer technique, many feature extractions have been formulated as a pyramid structure and then mapped into a binary tree. An efficient mapping from a tree structure into a pipelined array of 2logN stages is presented for processing an N*N image. In the proposed mapping structure, the identification of the information growing property allows the exploitation of bit-level concurrency in the architecture design. Accordingly, the design of each staged pipelined processor is simplified containing only bit-serial arithmetic. A single VLSI chip that can generate (p+1)(q+1) moments concurrently in real-time applications is described. This chip has a hardware complexity of O(pq(p+q)log/sup 2/N) units, where p, q stand for the orthogonal orders of the moment. This hardware complexity is better than the O(pq(p+q)/sup 2/log/sup 2/N) units required by the other methods. A single VLSI chip to generate ten moments for a (512*512*8)/pixel image in real time is presented.>