Several novel methods for the electrical-level simulation of digital VLSI MOS circuits on a shared-memory multiprocessor system are presented. A novel parallel algorithm, the overlapped phases algorithm, for the efficient simulation of circuits containing feedback loops, is presented. The algorithm is based on data flow scheduling and local relaxation of the feedback loops. A novel method for the partitioning of largepass transistor networks is discussed. The method is based on the signal flow direction in the elements. This partitioning allows an efficient simulation of these large networks on a multiprocessor system. Parallel element evaluation and the time segment pipelining method, two methods to increase the performance of the parallel circuit simulator, are explained. Simulation tests with actual circuits show a substantial acceleration for the new methods.>

This paper presents several new methods for the efficient parallel simulation of VLSI circuits that contain feedback loops or “difficult” parts such as arrays, registers and pass-transistor networks. A new parallel algorithm has been developed for the efficient simulation of circuits containing feedback loops. It is based on dataflow scheduling and local relaxation of the loops. For the simulation of large pass-transistor networks a partitioning method is used that is based on signal flow in the elements. Parallel element evaluation and time-segment pipelining are included to increase the performance of the parallel circuit simulator. Simulation tests with actual circuits show a substantial acceleration for the new methods.

The Segmented Waveform Relaxation Method (SWRM) is a new and efficient waveform relaxation method for circuit-level simulation of large-scale digital MOS networks. SWRM is original in two aspects. 1) Dynamic feedback loop cutting and waveform event driven scheduling result in a varying simulation order of the subcircuits and, for digital synchronous circuits, lead to logically correct and accurate ground waveforms in one waveform iteration where the only approximation is due to Miller feedback over MOS capacitances (timing error being usually <5 percent). 2) Dynamic decomposition of large subcircuits at MOS transistors which are temporarily in a nonconducting state. SWRM has been implemented in the program SWAN and tested on large industrial circuits (up to 4000 transistors) with speed gains of 10 /spl gt/ 100 over SPICE2G6. A mixed-mode switch electrical implementation of SWRM together with novel acceleration methods on parallel computers will be described together with test results on real-life circuits.