The performance benefits of vectorization are often limited by data movement, which remains a dominant bottleneck in modern processors. To mitigate this bottleneck, data stream-based mechanisms have been recently proposed, allowing general-purpose architectures to specialize memory accesses, leading to a reduction of load-to-use latency and loop code optimizations. However, compiler support for stream-based execution remains limited. Accordingly, this paper presents S2VEC, an LLVM-based compilation toolchain that automatically extracts, represents, and optimizes memory access patterns as data streams to enable stream-specialized vector execution. At its core, the Stream-Dataflow IR models computation as a dataflow over parameterized data streams, bridging the gap between conventional compiler infrastructures and stream-oriented architectures. By transforming complex and indirect memory accesses into linearized stream representations, S2VEC simplifies vectorization and expands its applicability to complex memory access patterns. When targeting a RISC-V stream-vector ISA extension, S2VEC demonstrates improved vectorization coverage and produces code comparable to hand-optimized implementations. Conducted evaluations on a gem5-based in-order stream-vector model show an overall speedup of 5.9 × over an equivalently provisioned RVV-based in-order core and 1.5 × over a wide out-of-order processor, demonstrating the performance benefits of compiler-driven stream specialization.

The massive adoption of IoT devices, the recent developments in the efficiency of AI systems, and the increase of edge computational power, accelerated the deployment of edge AI systems. The implementation of these systems through the use of low-power embedded devices scattered across the edges of a network allows for reduced latency and cost, compared to traditional cloud-based AI computing systems. As a result of the low-complexity AI models and the available low-power embedded systems on the market, this paper provides a comparative study on the inference performance of convolutional neural networks for different edge devices, by exploiting low-power GPUs and dedicated AI hardware. The benchmark results were able to achieve 864 inferences/s for the Jetson AGX Xavier board on a pre-trained SqueezeNet, while reaching a high power efficiency of 52.6 inferences/s per Watt. For the dedicated Movidius neural stick, the system requires only 1.5 W for processing 24.2 inferences/s.

Data movement between the main memory and the processor is a key contributor to execution time and energy consumption in memory-intensive applications. This data movement bottleneck can be alleviated using Processing-in-Memory (PiM). One category of PiM is Processing-using-Memory (PuM), in which computation takes place inside the memory array by exploiting intrinsic analog properties of the memory device. PuM yields high performance and energy efficiency, but existing PuM techniques support a limited range of operations. As a result, current PuM architectures cannot efficiently perform some complex operations (e.g., multiplication, division, exponentiation) without large increases in chip area and design complexity. To overcome these limitations of existing PuM architectures, we introduce pLUTo (processing-using-memory with lookup table (LUT) operations), a DRAM-based PuM architecture that leverages the high storage density of DRAM to enable the massively parallel storing and querying of lookup tables (LUTs). The key idea of pLUTo is to replace complex operations with low-cost, bulk memory reads (i.e., LUT queries) instead of relying on complex extra logic. We evaluate pLUTo across 11 real-world workloads that showcase the limitations of prior PuM approaches and show that our solution outperforms optimized CPU and GPU base-lines by an average of $713 \times$ and $1.2 \times$, respectively, while simultaneously reducing energy consumption by an average of $1855 \times$ and $39.5 \times$. Across these workloads, pLUTo outperforms state-of-the-art PiM architectures by an average of $18.3 \times$. We also show that different versions of pLUTo provide different levels of flexibility and performance at different additional DRAM area overheads (between 10.2% and 23.1%). pLUTo’s source code and all scripts required to reproduce the results of this paper are openly and fully available at https://github.com/CMU-SAFARI/pLUTo.

Unlike standard accelerators, the performance of Near-Data Processing (NDP) devices highly depends on the operation of the surrounding system, namely, the Central Processing Unit (CPU) and the memory hierarchy. Therefore, to accurately evaluate the gain provided by such devices, the entire processing system must be considered. Recent proposals redesigned existing architectural simulators to estimate the performance of NDP devices. However, the conclusions that can be drawn from using these frameworks are limited, and they fail to provide full support to simulate these devices (e.g., most simulators do not allow simultaneous operation of the CPU and the NDP device). In this paper, a novel framework (called gem5-ndp) based on the gem5 architectural simulator is proposed, providing full support to the development, validation, and evaluation of novel NDP architectures. To illustrate the process of developing and integrating an NDP device with a processing system using the proposed framework, as well as to demonstrate its viability and benefits, two case studies are also proposed and thoroughly discussed. gem5-ndp significantly improves the performance evaluation confidence of NDP devices with results showing that classical approaches lead to a deviation of up to 54.9 % when compared with results obtained with gem5-ndp.

Recently, there has been much interest in the use of convolutional neural networks (CNN) for mobile user localization in massive multiple-input multiple-output (MIMO) systems operating at millimeter wave (mmWave) frequencies. However, current CNN-based approaches cannot predict the confidence interval bounds for the localization accuracy. While the Bayesian neural network (BNN) method can be employed to estimate the model uncertainty, it entails a high computational cost. In this letter, the Monte Carlo (MC) dropout based method is proposed as a low-complexity approximation to BNN inference for capturing the uncertainty in a CNN-based mmWave MIMO outdoor localization system, without sacrificing accuracy. The proposed method is evaluated by means of simulations using a ray-tracing model of urban propagation at 28GHz. Results show that the localization uncertainty region can be properly determined and that their shape depends on the maximum power received at the user.

It is commonly perceived that an HLS specification targeted for FPGAs cannot provide throughput performance in par with equivalent RTL descriptions. In this work we developed a complex design of a non-binary LDPC decoder, that although hard to generalise, shows that HLS provides sufficient architectural refinement options. They allow attaining performance above CPU- and GPU-based ones and excel at providing a faster design cycle when compared to RTL development.

The polyphonic OpenMIC-2018 dataset is based on weak and incomplete labels. The automatic classification of sound events, based on the VGGish bottleneck layer as proposed before by the AudioSet, implies the classification of only one second at a time, making it hard to find the label of that exact moment. To answer this question, this paper proposes PureMic, a new strongly labelled dataset (SLD) that isolates 1000 single instrument clips manually labelled. Moreover, the proposed model classifies clips over time and also enhances the labelling robustness of a high number of unlabelled samples in OpenMIC-2018 due to its ability of classification over time. In the paper we disambiguate and report the automatic labelling of previously unlabelled samples. Our proposed new labels achieves a mean average precision (mAP) of 0.701 for OpenMIC test data, outperforming its baseline (0.66). We released our code online in order to follow the proposed implementation1.

This work explores the utilization of low-power heterogeneous devices for parallelizing the compute-intensive hyper-spectral and multispectral image compression CCSDS-123 entropy encoders. Multithread processing allows for the near-optimal system's bandwidth to be exploited increasing the system overall performance. The experimental platform consists of a low-power Jetson TX2 GPU equipped with an ARM Cortex-A57 and Denver 2 host processors, reporting more than 1552 Mb/s and, more importantly, 315 Mb/s/W, all running under a global 5 W power budget, which makes it a good candidate for onboard image compression.

With the advent of Big Data application domains, several Machine Learning (ML) signal-processing algorithms, such as Convolutional Neural Networks (CNNs), are required to process progressively larger datasets at a great cost in terms of both compute power and memory bandwidth. Although dedicated accelerators have been developed targeting this issue, they usually require moving massive amounts of data across the memory hierarchy to the processing cores and low-level knowledge of how data is stored in the memory devices to enable in-/near-memory processing solutions. In this paper, we propose and assess a novel mechanism that operates at cache level, leveraging both data-proximity and parallel processing capabilities, enabled by dedicated fully-digital vector Functional Units (FUs). We also demonstrate the integration of this mechanism in a conventional Central Processing Unit (CPU). The obtained results show that our engine provides performance improvements on CNNs ranging from 3.92× to 16.6×.

With 5G millimeter wave communications, the resulting radiation reflects on most visible objects, creating rich multipath environments. The radiation is thus significantly shaped by the obstacles it interacts with, carrying latent information regarding the relative positions of the transmitter, the obstacles, and the mobile receiver. Through a pre-estabilhed codebook of beamforming patterns transmitted by a base station, the concept of beamformed fingerprints for mobile devices' outdoor positioning has been previously proposed. In this paper, a tailored hierarchical convolutional neural network is proposed to further leverage the structure in the aforementioned hidden information. Average errors of down to 3.3 meters are obtained on a simulation environment based on realistic outdoor scenarios, containing mostly non-line-of-sight positions, making it a very competitive and promising alternative for outdoor positioning.

Monocular 3D reconstruction is a challenging computer vision task that becomes even more stimulating when we aim at real-time performance. One way to obtain 3D reconstruction maps is through the use of Simultaneous Localization and Mapping (SLAM), a recurrent engineering problem, mainly in the area of robotics. It consists of building and updating a consistent map of the unknown environment and, simultaneously, saving the pose of the robot, or the camera, at every given time instant. A variety of algorithms has been proposed to address this problem, namely the Large Scale Direct Monocular SLAM (LSD-SLAM), ORB-SLAM, Direct Sparse Odometry (DSO) or Parallel Tracking and Mapping (PTAM), among others. However, despite the fact that these algorithms provide good results, they are computationally intensive. Hence, in this paper, we propose a modified version of DSO SLAM, which implements code parallelization techniques using OpenMP, an API for introducing parallelism in C, C++ and Fortran programs, that supports multi-platform shared memory multi-processing programming. With this approach we propose multiple directive-based code modifications, in order to make the SLAM algorithm execute considerably faster. The performance of the proposed solution was evaluated on standard datasets and provides speedups above 40% without significant extra parallel programming effort.

Millimeter wave frequencies paired up with MIMO antennas employing beamforming are seen as critical enablers of next generation networks. However, selecting the most beneficial beamforming weights in a codebook-enabled downlink transmitter is a lengthy task, as the existing methods rely on some form of channel measurement. In fact, if the used codebook is too large, the traditional methods might fail to select an appropriate entry within the channel coherence time. In this paper, a new method to assist the beam selection is proposed, based on data obtained from previous connections. Through the continuous update of the set of optimal codebook entries for each position, the search space required for each connection can be greatly reduced if the user position is known. The simulations performed show that retrieving the sets of codebook entries in single user scenarios required less than 51 ns. For multi-user scenarios, results exceeding 10 simultaneous users using a 16 entry codebook were achieved, requiring less than 600 μs. The obtained results show that the proposed method can greatly reduce the beam selection latency and energy requirements, opening the door to powerful millimeter wave networks.

This paper proposes a low-cost workload distribution technique for the compute-intensive simulation of electron waves propagating in graphene superlattices, by fully exploiting the compute resources of heterogeneous GPUs concurrently. As old GPUs start failing and new ones are launched in the market, we equip our labs with more recent hardware, creating a variety of distinct GPU families that have non-negligent processing power available, but sometimes unused. Here we show how to exploit them with reduced parallel programming effort of the workload distribution on heterogeneous multi-GPU systems. The speedups obtained when comparing execution against uniform workload distribution (i.e. the same workload on each GPU) range from 1.2x up to 1.8x.

To reduce the average memory access time, most current processors make use of a multilevel cache subsystem. However, despite the proven benefits of such cache structures in the resulting throughput, conventional operations such as copy, simple maps and reductions still require moving large amounts of data to the processing cores. This imposes significant energy and performance overheads, with most of the execution time being spent moving data across the memory hierarchy. To mitigate this problem, a Cache Compute System (CCS) that targets memory-bound kernels such as map and reduce operations is proposed. The developed CCS takes advantage of long cache lines and data locality to avoid data transfers to the processor and exploits the intrinsic parallelism of vector compute units to accelerate a set of 48 operations commonly used in map and reduce patterns. The CCS was validated by integrating it with an MB-Lite soft-core in a Xilinx Virtex-7 VC709 Development Board. When compared to the MB-Lite core, the proposed CCS presents performance improvements in the execution of the commands ranging from 4x to 408x, and energy efficiency gains from 6x to 328x.

With millimeter wave wireless communications, the resulting radiation reflects on most visible objects, creating rich multi path environments, namely in urban scenarios. The radiation captured by a listening device is thus shaped by the obstacles encountered, which carry latent information regarding their relative positions. In this paper, a system to convert the received millimeter wave radiation into the device's position is proposed, making use of the aforementioned hidden information. Using deep learning techniques and a pre-established codebook of beamforming patterns transmitted by a base station, the simulations show that average estimation errors below 10 meters are achievable in realistic outdoors scenarios that contain mostly non-line-of-sight positions, paving the way for new positioning systems.

Applying advanced signal processing and artificial intelligence algorithms is often constrained by power and energy consumption limitations, in high performance and embedded, cyber-physical and super-computing devices and systems. Although Graphics Processing Units (GPUs) helped to mitigate the throughput-per-Watt performance problem in many compute-intensive applications, dealing more efficiently with the autonomy requirements of intelligent systems demands power-oriented customized architectures that are specially tuned for each application, preferably without manual redesign of the entire hardware and capable of supporting legacy code. Hence, this work proposes a new SCRATCH framework that aims at automatically identifying the specific requirements of each application kernel, regarding instruction set and computing unit demands, allowing for the generation of application-specific and FPGA-implementable trimmed-down GPU-inspired architectures. The work is based on an improved version of the original MIAOW system (here named MIAOW2.0), which is herein extended to support a set of 156 instructions and enhanced to provide a fast prefetch memory system and a dual-clock domain. Experimental results with 17 highly relevant benchmarks, using integer and floating-point arithmetic, demonstrate that we have been able to achieve an average of 140× speedup and 115× higher energy-efficiency levels (instructions-per-Joule) when compared to the original MIAOW system, and a 2.4× speedup and 2.1× energy-efficiency gains compared against our optimized version without pruning.

Least squares prediction is a technique used to foresee pixel values during image coding by finding the minimum square error of neighbouring pixels. It has shown considerable quality gains especially for complex images with high variations in pixel intensities. The drawback of this technique consists of high computational complexity, consuming the most significant part of processing time and resources available, which makes it difficult to implement in fast, lossy image coders. One challenge is therefore to reduce the computational time of this predictor, namely through the use of new parallel programming techniques, making it more attractive for state-of-the-art coder-decoders. Also, new algorithmic propositions are made, trying to reduce the time spent in exchange for rate-distortion performance. These propositions are senseful since this predictor is used not only in lossless image coding, but also in lossy as well. Another aim of this article is to analyze energy efficiency among different types of platforms for this signal processing algorithm. Comparisons are provided on parallel computing processors ranging from very powerful Graphics Computing Units (GPUs) to mobile General-Purpose GPUs.

Over the last years, deep learning architectures have gained attention by winning important international detection and classification challenges. However, due to high levels of energy consumption, the need to use low-power devices at acceptable throughput performance is higher than ever. This paper tries to solve this problem by introducing energy efficient deep learning based on local training and using low-power mobile GPU parallel architectures, all conveniently supported by the same high-level description of the deep network. Also, it proposes to discover the maximum dimensions that a particular type of deep learning architecture - the stacked autoencoder - can support by finding the hardware limitations of a representative group of mobile GPUs and platforms.

Computing on field-programmable gate arrays (FPGAs) has been receiving continued interest as it provides high performance at relatively low power budgets, while avoiding the high non-recurring engineering (NRE) costs associated with ASIC designs. However, FPGA development is typically performed using register transfer level (RTL) languages which make the design process protracted and error-prone when compared to software design flows. To ease these problems, high-level synthesis (HLS) tools have been introduced which abstract away the RTL architecture description from the designer. In this work we explore the design space of a nonbinary GF (q) low-density parity-check (LDPC) decoder using Vivado HLS and compare it with state-of-the-art RTL designs.

HLS tools have been introduced with the promise of easening and shortening the design cycle of tedious and error-prone RTL-based development of hardware accelerators. However, they do so either by concealing meaningful hardware decisions which model the computing architecture-such as OpenCL compilers-or by abstracting them away into a high-level programming language-usually C-based. In this paper, we show that although Vivado HLS is sufficiently mature to generate a functionally correct FPGA accelerator from a naive description, reaching an accelerator which optimizes the FPGA resource utilization in a way that conveys maximum performance is a process for a hardware architect mindset. We use a highly demanding application, that requires real-time operation, and develop a non-binary LDPC decoder on a state-of-the-art Virtex 7 FPGA, using the Vivado HLS framework. Despite using the same programming syntax as a C-language software compiler, the underlying programming model is not the same, thus, the optimizations required in code refactoring are distinct. Moreover, directive-based optimizations that tweak the synthesized C description hardware must be used in order to attain efficient architectures. These processes are documented in this paper, to guide the reader on how an HLS-based accelerator can be designed, which in our case can come close to the performance achieved with dedicated hand-made RTL descriptions.

Low-Density Parity-Check (LDPC) decoders typically implement a single decoding algorithm or update rule, which narrows down the design space of the decoder and maintains its overall simplicity. However, gear-shift techniques combine multiple decoding algorithms, update rules and quantization of the log-likelihood ratios (LLRs), allowing wider design space explorations as more parameters can be fine-tuned to a particular need. Gear-shift LDPC decoders have been shown to improve both the decoding throughput and the energy efficiency per bit decoded, while achieving similar capacity compared to traditional approaches that only use one algorithm. In this paper, we incorporate gear-shift techniques based on the Min-Sum algorithm (MSA) and Self-Corrected Min-Sum algorithm(SCMSA) using variable quantization steps. The proposed design allows bit error rate (BER) performances close to the more powerful SCMSA running only a selected number of iterations using the most powerful update rule.

Instead of measuring photo-similarity, SymStereo is a stereo vision algorithm that uses new cost functions to measure symmetry differences between pairs of images. In this paper we propose the acceleration of a complete signal processing pipeline for generating 3D volumes based on dense SymStereo. The outputs here generated achieve superior reconstruction quality namely for slant based scenarios, so typical in autonomous systems, that have to capture pairs of images and perform moving decisions in real-time. In particular, we analyse several parallelization strategies for the compute-intensive aggregation procedure using different parameters and evaluate a trade-off between processing time, and higher precision of the calculated depths and quality of the final reconstructed 3D volume. The developed parallel pipeline allows to process more than 4.5 volumes per second for high resolution images using commodity GPUs, which conveniently suits its application in a variety of robotics systems.

The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of special purpose VLSI implementations often need to explore parameters, such as optimal bitwidth and data representation, through time-consuming Monte Carlo simulations. A prominent example of this simulation-based exploration process is the design of decoders for error correcting systems, such as the Low-Density Parity-Check (LDPC) codes adopted by modern communication standards, which involves thousands of Monte Carlo runs for each design point. Currently, high-performance computing offers a wide set of acceleration options that range from multicore CPUs to Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). The exploitation of diverse target architectures is typically associated with developing multiple code versions, often using distinct programming paradigms. In this context, we evaluate the concept of retargeting a single OpenCL program to multiple platforms, thereby significantly reducing design time. A single OpenCL-based parallel kernel is used without modifications or code tuning on multicore CPUs, GPUs, and FPGAs. We use SOpenCL (Silicon to OpenCL), a tool that automatically converts OpenCL kernels to RTL in order to introduce FPGAs as a potential platform to efficiently execute simulations coded in OpenCL. We use LDPC decoding simulations as a case study. Experimental results were obtained by testing a variety of regular and irregular LDPC codes that range from short/medium (e.g., 8,000 bit) to long length (e.g., 64,800 bit) DVB-S2 codes. We observe that, depending on the design parameters to be simulated, on the dimension and phase of the design, the GPU or FPGA may suit different purposes more conveniently, thus providing different acceleration factors over conventional multicore CPUs.

Power and flexibility are important constraints in the design of new chips. The efficiency extracted from a design is increasingly becoming a dominant question, and several techniques and technological advances can be used to optimize efficiency in its energy and functionality domains. These two characteristics are critical in digital communication systems that must work accordingly with multiple communication standards at different power, throughput and latency requirements. In this work, we focus on the physical layer Forward Error Correcting (FEC) system, due to the tight throughput and latency constraints they are required to meet, and develop specialized processing engines for Low-Density Parity-Check (LDPC) codes decoding, a class of widely standardized codes. The engines were developed for execution on Field-Programmable Gate Array (FPGA) devices by exploring dataflow and wide-pipeline design approaches, and have the design flexibility to target different LDPC codes, since they were implemented using recent High-Level Synthesis (HLS) tools. The generated engines and architectures allow achieving highly efficient decoders with decoding throughputs ranging from 16 Mbit/s to 1.2 Gbit/s at energy efficiencies of 42 to 908 Mbit/Joule/iteration, while the achieved clock frequencies of operation vary from 80 to 300 MHz. Furthermore, our bandwidth analysis shows that workload boundaries do not impose limitations on a system bus.

Despite their ability to reach within the channel capacity in shorter codeblock lengths, non-binary LDPC codes have a higher decoding complexity that poses non-trivial barriers to their generalized adoption at algorithmic and compute-intensive levels. In this work, we propose a programmable FFT-SPA decoder that delivers high decoding throughput at low power consumptions, while retaining a design flexibility at the system level which surpasses typical VLSI descriptions, guaranteeing quick retargeting and prototyping of variants of this family of signal processing algorithms with effective decoding throughputs of up to 1 Mbit/s and potential throughputs of dozens of Mbit/s.

SymStereo is a new algorithm used for stereo estimation. Instead of measuring photo-similarity, it proposes novel cost functions that measure symmetry for evaluating the likelihood of two pixels being a match. In this work we propose a parallel approach of the LogN matching cost variant of SymStereo capable of processing pairs of images in real-time for depth estimation. The power of the graphics processing units utilized allows exploring more efficiently the bank of log-Gabor wavelets developed to analyze symmetry, in the spectral domain. We analyze tradeoffs and propose different parameter-izations of the signal processing algorithm to accommodate image size, dimension of the filter bank, number of wavelets and also the number of disparities that controls the space density of the estimation, and still process up to 53 frames per second (fps) for images with size 288 × 384 and up to 3 fps for 768 × 1024 images.

In medical ultrasound, synthetic aperture (SA) imaging is well-considered as a novel image formation technique for achieving superior resolution than that offered by existing scanners. However, its intensive processing load is known to be a challenging factor. To address such a computational demand, this paper proposes a new parallel approach based on the design of OpenCL signal processing kernels that can compute SA image formation in real-time. We demonstrate how these kernels can be ported onto different classes of parallel processors, namely multi-core CPUs and GPUs, whose multi-thread computing resources are able to process more than 250 fps. Moreover, they have strong potential to support the development of more complex algorithms, thus increasing the depth range of the inspected human volume and the final image resolution observed by the medical practitioner.

It is well known that non-binary LDPC codes outperform the BER performance of binary LDPC codes for the same code length. The superior BER performance of non-binary codes comes at the expense of more complex decoding algorithms that demand higher computational power. In this paper, we propose parallel signal processing algorithms for performing the FFT-SPA and the corresponding decoding of non-binary LDPC codes over GF(q). The constraints imposed by the complex nature of associated subsystems and kernels, in particular the Check Nodes, present computational challenges regarding multicore systems. Experimental results obtained on GPU for a variety of GF(q) show throughputs in the order of 2 Mbps, which is far above from the minimum throughput required, for example, for real-time video applications that can benefit from such error correcting capabilities.

Aberrant crypt foci (ACF) are thought to be one of the earliest manifestations of colorectal cancer (CRC). We propose a parallel signal processing algorithm (based on a fast approach of the active contour without edges model) to segment in vivo ACF, from stained endoscopic images, to serve as a diagnosis/prognosis auxiliary. In order to tackle this challenge, we successfully overcame several obstacles, involving the adaptation of the algorithm and data structures to a parallel environment. This algorithm was developed using the compute unified device architecture (CUDA) interface, which allows programming the graphics processing units (GPU). We show that it is possible to process four frames of 1 Mega pixel images per second using a conventional GPU. The GPU speeds up the in vivo ACF segmentation more than 40×, regarding to CPUs, and paves the way for real-time segmentation.

The tradeoff between error-correcting performance and numerical complexity of LDPC decoding algorithms is a well-known problem. In this paper we depict the unseen error-floor performance of the Self-Corrected Min-Sum algorithm for long length DVB-S2 codes. We developed a massively parallel simulation using GPUs which allowed a comprehensive BER characterization either in the waterfall or in the error-floor region. We show that the self-correction technique increases the BER performance by 0.5 and 0.2 dB, in the waterfall and error-floor region, when compared to the Min-Sum algorithm. Furthermore, it reaches within 0.2 dB to the Logarithmic Sum-Product BER performance and it also outperforms the Normalized Min-Sum at high SNR, a low complexity decoding algorithm which yields good BER performance.

Estimating the amount and center of distortion from lines in the scene has been addressed in the literature by the so-called ``plumb-line'' approach. In this paper we propose a new geometric method to estimate not only the distortion parameters but the entire camera calibration (up to an ``angular'' scale factor) using a minimum of 3 lines. We propose a new framework for the unsupervised simultaneous detection of natural image of lines and camera parameters estimation, enabling a robust calibration from a single image. Comparative experiments with existing automatic approaches for the distortion estimation and with ground truth data are presented.

Hardware designers and engineers typically need to explore a multi-parametric design space in order to find the best configuration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips need to explore parameters such as the optimal bit width and data representation. This is the case for the development of complex algorithms such as Low-Density Parity-Check (LDPC) decoders used in modern communication systems. Currently, high-performance computing offers a wide set of acceleration options, that range from multicore CPUs to graphics processing units (GPUs) and FPGAs. Depending on the simulation requirements, the ideal architecture to use can vary. In this paper we propose a new design flow based on Open CL, a unified multiplatform programming model, which accelerates LDPC decoding simulations, thereby significantly reducing architectural exploration and design time. Open CL-based parallel kernels are used without modifications or code tuning on multicore CPUs, GPUs and FPGAs. We use SOpen CL (Silicon to Open CL), a tool that automatically converts Open CL kernels to RTL for mapping the simulations into FPGAs. To the best of our knowledge, this is the first time that a single, unmodified Open CL code is used to target those three different platforms. We show that, depending on the design parameters to be explored in the simulation, on the dimension and phase of the design, the GPU or the FPGA may suit different purposes more conveniently, providing different acceleration factors. For example, although simulations can typically execute more than 3× faster on FPGAs than on GPUs, the overhead of circuit synthesis often outweighs the benefits of FPGA-accelerated execution.

Low-Density Parity-Check (LDPC) codes are powerful error correcting codes used today in communication standards such as DVB-S2 and WiMAX to transmit data inside noisy channels with high error probability. LDPC decoding is computationally demanding and requires irregular accesses to memory which makes it suitable for parallelization. The recent introduction of the many-core Single-chip Cloud Computer (SCC) from Intel research Labs has created new opportunities and also new challenges for programmers that wish to exploit conveniently the high level of parallelism available in the architecture. In this paper we propose three different implementations: a distributed, a shared and a multi-codeword implementation, for LDPC decoding algorithms that explore the Intel SCC scaling opportunities. From the experimental results we observed that the distributed memory model couldn't scale due to the large number of messages exchanged by the parallel kernels, while the shared memory model had a limited scaling due to the overhead added by the uncacheable shared memory. On the other hand, the multi-codeword implementation scales almost linearly acheving a relative throughput of 28 for 32 cores.

It is well known that LDPC decoding is computationally demanding and one of the hardest signal operations to parallelize. Beyond data dependencies that restrict the decoding of a single word, it requires a large number of memory accesses. In this paper we propose parallel algorithms for performing in CPUs the most demanding case of irregular and long length LDPC codes adopted in the Digital Video Broadcasting Satellite 2 (DVB-S2) standard used in data communications. By performing simultaneous multicodeword decoding and adopting special data structures, experimental results show that throughputs superior to 90 Mbps can be achieved when LDPC decoders for the DVB-S2 are implemented in the current CPUs.

Unlike usual VLSI approaches necessary for the computation of intensive Low-Density Parity-Check (LDPC) code decoders, this paper presents flexible software-based LDPC decoders. Algorithms and data structures suitable for parallel computing are proposed in this paper to perform LDPC decoding on multicore architectures. To evaluate the efficiency of the proposed parallel algorithms, LDPC decoders were developed on recent multicores, such as off-the-shelf general-purpose x86 processors, Graphics Processing Units (GPUs), and the CELL Broadband Engine (CELL/B.E.). Challenging restrictions, such as memory access conflicts, latency, coalescence, or unknown behavior of thread and block schedulers, were unraveled and worked out. Experimental results for different code lengths show throughputs in the order of 1 \sim 2 Mbps on the general-purpose multicores, and ranging from 40 Mbps on the GPU to nearly 70 Mbps on the CELL/B.E. The analysis of the obtained results allows to conclude that the CELL/B.E. performs better for short to medium length codes, while the GPU achieves superior throughputs with larger codes. They achieve throughputs that in some cases approach very well those obtained with VLSI decoders. From the analysis of the results, we can predict a throughput increase with the rise of the number of cores.

In this paper we propose to show how signal processing algorithm designers can understand the nuances of multicore computing engines in order to conveniently exploit these powerful devices. This is illustrated by presenting source and channel coding, two fundamental operations in multimedia signal processing. We describe methods and principles to develop parallel signal processing algorithms to compute motion estimation for advanced video coding, and low-density parity-check code decoding for forward error correction in the channel coding context. The paper will consider general purpose multi-core architectures and accelerators such as the Cell/B.E. and graphics processing units. Experimental evaluation of the multi-core systems allows their performance for signal processing applications to be compared side by side with previous hardware dedicated solutions.

Due to huge computational requirements, powerful Low-Density Parity-Check (LDPC) error correcting codes, discovered in the early 1960s, have only recently been adopted by emerging communication standards. LDPC decoders are supported by VLSI technology, which delivers good parallel computational power with excellent throughputs, but at the expense of significant costs.

Low-Density Parity-Check (LDPC) codes are among the best error correcting codes known and have been adopted by data transmission standards, such as DVB-S2 or WiMax. They are based on binary sparse parity check matrices and usually represented by Tanner graphs. LDPC decoders require very intensive message-passing algorithms, also known as belief propagation. This paper proposes a very compact stream-based data structure to represent such a bipartite Tanner graph, which supports both regular and irregular codes. This compact data structure not only reduces the memory required to represent the graph but also puts it in an appropriate format to gather data into streams. This representation also allows to map the irregular processing behavior of the Sum Product Algorithm (SPA) used in LDPC decoding into the stream-based computing model. Stream programs were developed for LDPC decoding and the results show significant speedups obtained either using general purpose processors, or graphics processing units. The simultaneous decoding of several codewords was performed using the SIMD capabilities of modern stream-based architectures available on recent processing units.

Low-Density Parity-Check (LDPC) codes are powerful error correcting codes (ECC). They have recently been adopted by several data communication standards such as DVB-S2 and WiMax. LDPCs are represented by bipartite graphs, also called Tanner graphs, and their decoding demands very intensive computation. For that reason, VLSI dedicated architectures have been investigated and developed over the last few years. This paper proposes a new approach for LDPC decoding on graphics processing units (GPUs). Efficient data structures and an new algorithm are proposed to represent the Tanner graph and to perform LDPC decoding according to the stream-based computing model. GPUs were programmed to efficiently implement the proposed algorithms by applying data-parallel intensive computing. Experimental results show that GPUs perform LDPC decoding nearly three orders of magnitude faster than modern CPUs. Moreover, they lead to the conclusion that GPUs with their tremendous processing power can be considered as a consistent alternative to state-of-the-art hardware LDPC decoders.

State-of-the-art decoders for Low-Density Parity-Check (LDPQ codes adopted by the DVB-S2 standard, explore the periodicity M = 360 features of the selected special LDPC- IRA codes. This paper addresses the generalization of a well known M-kernel parallel hardware structure and proposes an efficient partitioning by any factor of M, without memory addressing overhead and keeping unchanged the efficient message mapping scheme. The method provides a simple and efficient way to reduce the decoder complexity. Synthesizing the proposed decoder architecture for N = {45,90,180} parallel processing units using an FPGA family from Xilinx shows a minimum throughput above the minimal 90 Mbps.