The timing optimization of multiphase logic entails the reduction of the overall cycle time of the machine and/or input-to-output delays by distributing computation throughout the entire clock cycle. A tool has been developed to automatically perform this optimization task, and it has been implemented as a set of extensions to the combinational logic optimization tool, misII. The algorithms yield improvements that are on average 10-20% better than what is achievable using purely combinational logic optimization tools that do not move logic across latches. These improvements represent 75% of what would be possible in the most idealized case. Results on simple two-phase circuits show average input-to-output delay improvements of 13% with area penalties of 11%. For a four-phase controller used in the SPUR processor it yields an improvement in cycle time of 18% with an area penalty of 11%. Experiments indicate that the optimization algorithm is highly insensitive to parameter variations in the underlying combinational logic optimization routines and initial state assignment.>

An approach is described for the minimization of multilevel logic circuits. A multilevel representation of a block of combinational logic is defined, called a Boolean network. A procedure is then proposed, called ESPRESSOMLD, to transform a given Boolean network into a prime, irredundant, and R-minimal form. This procedure rests on the extension of the notions of primality and irredundancy, previously used only for two-level logic minimization, to combinational multilevel logic circuits. The authors introduce the concept of R-minimality, which implies minimality with respect to cube reshaping, and demonstrate the crucial role played by this concept in multilevel minimization. Theorems are given that prove the correctness of the proposed procedure. Finally, it is shown that prime and irredundant multilevel logic circuits are 100% testable for input and output single-stuck faults, and that these tests are provided as a byproduct of the minimization.>

Article Free Access Share on SOCRATES: a system for automatically synthesizing and optimizing combinational logic Authors: David Gregory GE Calma Company Research Triangle Park, North Carolina GE Calma Company Research Triangle Park, North CarolinaView Profile , Karen Bartlett Department of Electrical Engineering University of Colorado at Boulder Department of Electrical Engineering University of Colorado at BoulderView Profile , Aart de Geus GE Calma Company Research Triangle Park, North Carolina GE Calma Company Research Triangle Park, North CarolinaView Profile , Gary Hachtel Department of Electrical Engineering University of Colorado at Boulder Department of Electrical Engineering University of Colorado at BoulderView Profile Authors Info & Claims DAC '86: Proceedings of the 23rd ACM/IEEE Design Automation ConferenceJuly 1986 Pages 79–85Online:02 July 1986Publication History 32citation279DownloadsMetricsTotal Citations32Total Downloads279Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

The automation of the synthesis and optimization of combinational logic can result in savings in design time, significant improvements of the circuitry, and guarantee functional correctness. Synthesis quality is often measured in terms of the area of the circuit on the chip, which fails to take into account the timing constraints that might be imposed on the logic. This paper describes SOCRATES, a synthesis system capable of generating combinational logic in a given technology under user-defined timing constraints. We believe this system is the first to perform optimized, delay-constrained, multilevel synthesis into standard cell libraries. Applied to a large number of examples, the system has successfully traded off area versus delay and performs optimized, delay-constrained, multilevel synthesis into standard cell libraries.