In this paper, we examine delay models used in very large scale integration (VLSI) circuit testing. Our study is based on electrical-level simulation experiments. We present a comprehensive analysis of phenomena which significantly affect the actual delays but are not taken into account by the existing models used in testing. Because of these phenomena, for a given path in a circuit, tests commonly considered equivalent may result in different pass/fail decisions. Moreover, contrary to a common assumption, robust tests may fail to detect faults detectable by nonrobust tests. This may happen even in circuits in which all paths are robust testable. Our analysis questions the test quality offered by delay test procedures used so far.

We show that a path delay under a non-robust test may be longer than under any robust test. Thus, for a given path, a non-robust test can detect a delay fault undetectable by robust tests. This can happen even in a circuit in which all paths are robust-testable.

We propose simple modifications to existing BIST schemes. These modifications significantly improve the path delay fault coverage. For example, a modified circular self-test path can detect a significant number of path delay faults within a reasonable test running time.>

Proposes a new easily testable PLA. In the design process the authors use a simple property of relatively prime numbers. The PLA can be efficiently integrated with random pattern techniques used for testing combinational circuits. In the proposed implementation, test pattern generation and test response compaction are performed by circular self-test path (circular BIST). Very high fault coverage can be achieved in a feasible testing time.>