Demo Data from EDBT 2026 / reviewers in the wild / expert
Hiroshi Niitsu
dblp:03/2342
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 1997
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2Theory of computation · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 75% Reconfigurable computing and FPGAs · 25% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Reconfigurable computing and FPGAs
FPGA architecture |
0.0 | 1 | 1997 | Design of minimum and uniform bipartites for optimum connection blocks of FPGA · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997 |
Electronic design automation
physical design |
0.0 | 1 | 1997 | Design of minimum and uniform bipartites for optimum connection blocks of FPGA · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997 |
Electronic design automation › physical design
routing |
0.0 | 1 | 1997 | Design of minimum and uniform bipartites for optimum connection blocks of FPGA · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997 |
Electronic design automation › physical design › routing › FPGA routing
switch box design |
0.0 | 1 | 1997 | Design of minimum and uniform bipartites for optimum connection blocks of FPGA · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997 |
Methods — techniques the papers use, named apart from their topics
bipartite graph construction · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1997 | Design of minimum and uniform bipartites for optimum connection blocks of FPGAabstractThe design of optimum connection blocks of field programmable gate arrays (FPGA's) in number and in distribution of switches is formulated as a bipartite graph design problem and solved. A bipartite with vertex sets R and L (|R|/spl les/|L|) is called totally perfect if there is a perfect matching from L/sub s/ to R for any L/sub s//spl sub/L with |L/sub s/|/spl les/|R|. The difference of maximum and minimum degrees of the vertices in L or R is called the skew of the respective vertex set. The problem is to construct a minimum totally perfect bipartite graph with the minimum skew. The result shows that a method, biscattering, can construct such a matrix in O(|R|/spl times/|L|) time where the lower bound is attained for both skews. This construction also solves the problem of designing optimum direct-concentrators. Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 1994 | The Totally-Perfect Bipartite Graph and Its Construction
Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu |
ISAAC | 3 |
| 1994 | Design of Optimum Totally Perfect Connection-Blocks of FPGAabstractThe optimal design problem of the connection-blocks of FPGA with respect to the number of switches and their distribution is solved. This also concerns with the optimal construction of direct concentrators.> Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu |
ISCAS | 3 |