This research explores the employment of Reduced Precision Redundancy (RPR) as a power saving alternative to traditional Triple Modular Redundancy (TMR). This paper focuses on the details of RPR implementation and the effect of RPR fault tolerance on the performance of spacecraft systems. RPR-protected system performance is evaluated using a signal-to-noise ratio analogy developed with Matlab and Simulink computational tools. This research demonstrates that RPR is an effective fault tolerance approach for arithmetic operations. Experimental results show that the benefit of RPR increases with the complexity of the operation to which it is applied. System performance simulations demonstrate that RPR provides very good recovery from errors caused by SEE in spacecraft systems.

Real-time cyclic spectral analysis is useful in many applications, but is difficult to achieve because of its computational complexity. This paper studies the distribution of complex multipliers in multiprocessor cyclic spectrum analyzers, with the objective of obtaining computational balance. Computationally balanced implementations efficiently use hardware so that computational bottlenecks are reduced and a smooth flow of data between computational sections of the analyzer is maintained. Tables are presented that give the number of complex multipliers required in each section of the analyzer to obtain computational balance.>

This paper is concerned with the high rate realization of finite-state machines. Two new techniques for high rate realization of finite-state machines are presented, one applicable to finite, the other to infinite memory span machines. It is found that any finite-state machine can be realized by a tree of component machines of a proper size with a given high rate, where the propagation delay of the component machine is less than or equal to the reciprocal of the given high rate. For a given set of logic devices, a synthesis procedure for the component machine with a given propagation delay is proposed.

In this paper we concern ourselves with the problem of obtaining high sequence rate sequential machines, machines which are constructed from realistic devices to operate at an input sequence rate which is independent of the machine complexity. To accomplish this result we have only to show a construction to realize acceptably synchronous devices from badly timed, restricted fan-in and fan-out devices. Once a complete set of synchronous devices is obtained, the results of Arden and Arthurs [ 11 apply and we know that any finite state machine has a realization using these devices which accepts input sequence members at a rate which is characteristic of the set of devices, not of the machine. The technique we propose for achieving this result is to produce a lattice of interconnected clock pulse sources called clock pulse propagators (CPPs). These devices generate clock pulses which are acceptably synchronized with respect to the outputs of neighboring CPPs but are not required to be in synchronization with some machine-wide standard as in current practice. Once it is established that such a network is possible, techniques already known can be applied in the utilization of the clock- pulses to synchronize logic and signals. Part I1of the paper concerns the analysis of CPP networks, and Part II covers the synthesis of sequential machines using CPP networks as clocking sources.

In this paper we concern ourselves with the problem of obtaining high sequence rate sequential machines; machines which are constructed from realistic devices to operate at an input sequence rate which is independent of the machine complexity. To accomplish this result we have only to show a construction to realize acceptably synchronous devices from badly timed, restricted fan-in and fan-out devices. Once a complete set of synchronous devices is obtained, the results of Arden [1] and Arthurs [2] apply, and we know that any finite state machine has a realization using these devices which accepts input sequence members at a rate that is characteristic of the set of devices, not of the machine. The technique we propose for achieving this result is to produce a lattice of interconnected clock pulse sources called clock pulse propagators (CPP). These devices generate clock pulses which are acceptably synchronized with respect to the outputs of neighboring CPP's but are not required to be in synchronization with some machine-wide standard as in current practice. Once it is established that such a network is possible, techniques already known can be applied in the utilization of the clock pulses to synchronize logic and signals. Part I of the paper concerns the analysis of CPP networks and Part II1covers the synthesis of sequential machines using CPP networks as clocking sources.

This paper concerns the application of a result of Arden and Arthurs to a particular finite-state machine, the accumulator. Arden and Arthurs have shown that given a complete set of devices for some fixed sequence rate, any finite-state machine may be constructed from these devices to operate at this maximum rate. In this paper we consider the construction of a good representation (in terms of overall delay) of the m-bit accumulator, operating at the maximum rate. Examples are presented using state-of-the-art devices which illustrate the construction and give measures of usefulness and cost Of this accumulator.

This paper concerns a property of sets of delayed-logic devices. This property, called completeness, characterizes sets of logic devices that can be used for the construction of networks to represent any finite-state machine. Associated with this property is a rate of completeness, which is the maximum input sequence rate for which any finite-state machine can be constructed from the given set of devices. Tests for completeness are presented from which the completeness or lack thereof may be determined for certain classes of sets of devices. For complete sets of devices, these tests also determine the rate of completeness.

A complete set of logic primitives is a set of devices which can be connected to represent any Boolean function of binary variables. This paper deals with the number of devices required in a complete set of logic primitives. It is well known that a complete set of logic primitives may contain as few as one element, e.g., NOR. It is the purpose of this paper to establish a least upper bound on the number of nonredundant elements in a complete set. It is shown that every complete set contains a complete subset with at most four elements. Further, a complete set with four elements is presented which is incomplete if any element is deleted.