x86 technology has become the standard processor building block of high performance computing. With each new generation of x86, significant performance improvements have occurred. In the past, frequency was the key to this increasing performance. Today, it is a combination of systems architecture and multi-core support. As a result, the bandwidth and latency of both the chip level interconnect and memory have become the keys to increasing chip level performance. Mr. Oehler will discuss both the challenges and solutions in maximizing chip level interconnect and memory efficiencies, citing examples from AMD's development and advancement of the Direct Connect Architecture and integrated memory controller. He will specifically highlight the details associated with the development of next-generation quad-core processors, including the substantial evolution of the Direct Connect high-speed I/O infrastructure and memory access structures. As the number of cores continue to increase, the challenges and possible future solutions will also be discussed.