This paper presents a symmetric correlated coding (SCC) scheme and the corresponding high-density transceiver that deliver 7-bit data over 8 lanes. The SCC method implements the 7-bit data encoding jointly in 8 correlated channels which improves the pin efficiency up to 87.5%. Besides, as an advanced chord signaling, the SCC exhibits the immunity to crosstalk, common-mode noise (CMN) and simultaneous switching noise (SSN). The proposed SCC transceiver innovates a SCC source-series-terminated (SST) driver that maintains an unchanged bandwidth even with a low-voltage power supply, and the CTLE decoder adopts the active inductor to compensate the channel loss. Prototyped in 28-nm CMOS, the proposed wireline transceiver using SCC method supports a maximum data rate of$7\times 10$Gb/s with a bit error rate (BER) <1e−12, achieving a data rate density (DRD) up to 61.4 Gb/s/mm. The SCC transceiver dissipates 99.4 mW with the energy efficiency of 1.42 pJ/bit.

This paper proposed a wireless 16-channel im-plantable system for long-term neural recording. In order to achieve stable and reliable neural signal acquisition, the im-plantable microsystem consists of an analog front end (AFE), a transmitter (TX), a small battery and a coil for energy harvesting to charge the battery. The AFE integrates 16-channel low-noise amplifiers (LNA), a SAR ADC and a digital interface. The TX integrates a rectifier, a bandgap voltage reference, regulators and a 427 MHz OOK modulated transmitter. The AFE and TX chips were fabricated in 180-nm technology. All the required functional modules are integrated in the chips with off-chip crystal, coil and antenna. The proposed microsystem weighs 2.1 g without a battery, and 3.7 g including the battery. The dimension is$20\times 18\times 7$mm 3. The total current of the system is 1.13 mA, and the battery life is about 50 hours with a capacity of 60 mA$h$. The charging current is 10mA under wireless power transmission.

This paper proposed a miniature neural interface system. A single chip neural recording SoC was fabricated in 40nm CMOS process with an area of 3mm×3mm. It integrated a 16-channel analog front end (AFE), and a low power constant envelope polar transmitter. The general form of continuous phase modulation was used as the modulation scheme. Algorithms for receiver including frequency offset calibration, frame synchronization, and symbol demodulation were proposed and implemented on a software-defined radio platform. Simulation results showed that a bit error rate of $10^{-4}$ is achieved at the signal to noise ratio of 19 dB at high data rate mode of 971.4 kbps. A graphic user interface was designed for channel decoding and real-time display. Experimental results showed that the input referred noise of the AFE is 2.87$\mu V_{rms}$, and the energy efficiency of the transmitter is 2. 8nJ/bit. The proposed chip consumes 5. 47mW power in total in its maximum workload. The neural signal can be correctly decoded at least at a RSSI (Received Signal Strength Indicator) of -95dBm, and a working distance of 8 m. In-vivo tests on rat have been conducted, showing a good usability of the proposed system.

This paper proposed a fully integrated MBAN (2360–2400 MHz) continuous phase modulated transmitter (TX) with tunable less than 0dBm output power for medical band. A duty-cycle tuning strategy was proposed for the power amplifier (PA) featuring adaptive optimized efficiency for different output powers. A fully on-chip transformer-based match network was proposed to suppress the 2nd harmonic using a series$LC$resonator and to suppress the 3rd harmonic by introducing a transformer inter-winding capacitor feedback path. A fractional-N all-digital phase locked loop (ADPLL) with a transformer-based digitally controlled oscillator (DCO) is employed to reduce power consumption as well as improve modulation quality. The transmitter was fabricated in 40-nm CMOS technology, occupying an active area of 0.48mm2. Experimental results show a 26% drain efficiency with −10dBm PA output and 4dB tunable range. A 2mW total power consumption was measured with a TX efficiency of 5% and an energy efficiency of 2nJ/bit. The measured 2nd and 3rd harmonic distortion of the output were −44.3dBm and −57.2dBm, respectively, with on-chip matching network. The measured FSK error of CPM was 2.3% with an M of 2 and 1.57% with an M of 4.