Wireless Sensor Networks (WSNs) are particular networks characterized by limited energy and computational resources and, if their transmission range is limited to a person's area, they are known as Body Area Networks (BANs). When two or more BANs are co-located and operate on the same channel, active periods can overlap and transmissions can conflict. This phenomenon, that drastically reduces performances and reliability of BANs, is known as BAN-BAN interference. In order to solve this issue, it is possible to employ techniques such as channel switching. However, channel switching is not suitable if the amount of channels is lower than the amount co-located BANs and, considering that interferences of Zigbee/802.15.4 networks with other technologies like 802.11 or Bluetooth reduce the amount of channels available for communication, an alternative approach is required. This paper introduces a BAN-BAN Interference Reduction System (B2IRS) which reschedules beacon packets in order to avoid active period overlap, reducing the interferences between distinct BANs. This approach is complementary to channel switching since it works with single-channel interferences, that arise when no free channels are available anymore. Experimental results, conducted comparing our methodology with the original IEEE 802.15.4, show that B2IRS is able to effectively reduce BAN-BAN interference, making it possible to almost maintain the same performance and energy consumption of an ideal situation (without interferences).

Wireless sensor networks (WNSs) are gradually evolving from a promising technology to a well-established reality in a large set of different domains. In order to fulfill the requirements of the specific scenario, a WSN must provide the right tradeoff between performance and lifetime, which is heavily determined by the network design. However, although the complexity of WSNs is increasing, the design space exploration is often carried out manually without the support of a general analytical methodology. In this paper, we advocate a model-based approach as an efficient and scalable way to explore the energy-performance tradeoffs during the design. In particular, we show that it is possible to define system-level models to describe wide classes of WSNs, providing a quick and accurate network evaluation. As a proof of concept, we propose a general model that describes the main characteristics of a class of WSNs for human health monitoring, and we apply it to a real case study. The results show that the energy-performance estimation error of the model never exceeds 1.74% compared to real data, while the evaluation time is reduced by up to 6 orders of magnitude with respect to an accurate network simulation.

The use of Field Programmable Gate Array (FPGA) based System on Chip (SoC) is a promising approach in Multimedia applications. In SoC, computationally intensive tasks are off-loaded to the hardware logic. A feature introduced with new FPGA devices, Dynamic Partial Reconfiguration (DPR) is suitable to change this hardware logic when needed and while the rest of the system continues its functioning. As the applications running on hardware logic are real-time and computationally intensive, in order to make use of DPR to change the hardware logic, the efficiency of the DPR process is crucial. This paper describes how a FPGA-based Multimedia Application (Audio-Video filtering), benefits from dynamic partial reconfiguration and a custom DPR controller: the Speed Efficient Dynamic Partial Reconfiguration Controller (SEDPRC). Experimental results have shown that the novel controller brings benefits to the reconfiguration time. Enhancements in reconfiguration throughput up to a 55× factor are achieved.

This paper introduces Tacit Consent (TaCo), a technique that exploits spatial correlation in Wireless Sensor Networks in order to reduce energy consumption while maintaining a very high accuracy on the measured data. In fact, nodes densely deployed in a field of interest are proved to sense highly correlated data, thus this intrinsic redundancy can be exploited to predict the neighbors' measurements by defining custom estimation functions, which aim at replicating the relationship between the data sensed by two nodes. To exploit spatial correlation, TaCo splits the nodes into two groups: representative and member nodes. Representative nodes directly transmit their measurements, while member nodes use overhearing to understand whether additional information is required. If the estimation function correctly predicts the measurements of the member nodes, they tacitly consent the estimation without performing any transmission. Differently from the other state-of-the-art approaches, such as the YEAST algorithm, TaCo can be used on top of existing routing and clustering protocols. Experimental results prove that TaCo is able to drastically reduce the energy consumption of the network when a high precision of the measured data is required.

Wireless sensor networks (WSNs) are networks of battery-powered sensing devices connected with wireless interfaces. Energy consumption and processing efficiency are relevant characteristics for these systems, thus energy-efficient architectures are required. Recent works show that FPGAs are suitable candidates for efficient data signal processing in WSNs. In this work, we evaluate Flash-based FPGA technology for WSNs' applications, and we present FPGA-based architecture for data signal processing in WSN's nodes. Low static power consumption of Flash-FPGAs is a fundamental characteristic in WSNs systems, which are characterized by long idle periods. SRAM-based and Flash-based FPGAs were compared, and an architecture to manage dynamic energy consumption in Flash-based FPGAs is presented. The architecture has been validated and evaluated on a real testbed, and power consumption results are presented. In our experiments, the overall power consumption of the FPGA is kept below 4mW.

Nowadays, the Network-on-Chip (NoC) paradigm has become more and more popular for building an on-chip communication infrastructure. Like in every traditional network, debugging and performance monitoring are also very important issues in NoC-based systems. Unfortunately, the design process of monitoring hardware is a time consuming activity. The work presented in this paper is based on a high level specification language, called SiLLis (Simplified Language for Listeners), for the convenient development of generic monitoring hardware. SiLLis allows the designer to define complex filter rules on a high abstraction level. In this way, the design time as well as the bandwidth requirements for monitoring data can be drastically reduced. To present the benefits of SiLLis, we define a performance monitor that is integrated into a NoC-based multiprocessor System-on-Chip and can be used both to analyze the performance of the system and to optimize the routing strategy at run-time. By using SiLLis, the performance monitor can be realized with a area overhead of only 0.58 % per NoC node.